Uegent! Regarding Busy signal from ADC to interact with SPI

[LF_LF]

HI, everybody.
For my project, i need to create a SPI to interact between DE2 board and ADC(ADS7861). I have created one but i think iy wouldn't work due to busy line and my approach.
My approach is that i use the estimation approach where i use clock cycle to calculate the data conversion process, when it finish and and data arrive. For Example, according to datasheet of ADS7861 ADC, Serial Data A will be available after 2 clock cycles of conversion start. Then after 12 bits of valid data, it has 2 bits flag which is 00 to indicate end of 1 conversion cycle. Therefore, i use this to calculate and design my VHDL code.
Well, another reason for me not using the busy signal is because i really no idea how to use it as it will only trigger to low 3 bits before end of 1 conversion cycle then the valid data has 12 bits to be transfered to my DE2 board. That's mean it need 12 clock cycle for the DE2 board to receive it, right? of course, this 12 clock cycles need to accept 12 bits data is using counter, but i have no idea what else approach to use to receive these 12 bits data if i didn't use counter to loop for receiving.

Now, after tested with hardware, i cant obtain the serial data output from ADC. Maybe due to this estimation method i used that miss the accuracy of clock cycles.

Can anybody let me know the ways to obtain the data using Busy signal from ADC? The serial data valid only up to 1ns after rising edge of next clock. That's mean only has maximum 3 clock cycles + 1ns or even less to attach all 12 bits valid data from ADC.
Please anybody please give me a hand. The due data for this is end of this week.
Thank you in advanced.

 

[FvM]

Re: Uegent! Regarding Busy signal from ADC to interact with

Your post sounds really confused. According to the datasheet, the busy signal doesn't help you in determining the correct
timing for read data.

Your considerations about receive time margin are very unclear. Typically, the serial data is sampled on the falling clock edge.
Clearly you have to count data bits correctly related to conversion start. As the clock is continuously running, you can also read
the data continuously to the DATA A/B shift registers. You have to determine the correct cycle, when to latch the shift register to
the parallel data output, that's all.

The timing specification suggests, that a new conversion can be started on each 16th clock cycle, which leads to a simple timing scheme.

 

[LF_LF]

Re: Uegent! Regarding Busy signal from ADC to interact with

Your post sounds really confused. According to the datasheet, the busy signal doesn't help you in determining the correct
timing for read data.

Your considerations about receive time margin are very unclear. Typically, the serial data is sampled on the falling clock edge.
Clearly you have to count data bits correctly related to conversion start. As the clock is continuously running, you can also read
the data continuously to the DATA A/B shift registers. You have to determine the correct cycle, when to latch the shift register to
the parallel data output, that's all.

The timing specification suggests, that a new conversion can be started on each 16th clock cycle, which leads to a simple timing scheme.

Hi, FvM.
Sorry to confuse you guys.
My design is based on clock cycle of ADC. The data conversion need 16 clock cycles, thus i design a VHDL module/block for conversion start to high every 16 clock cycles.Then, the serial data output has 16bits data where first 2 and last 2 are not valid data, valid data is the medium 12 bits.
By refer to clock cycles, i design a VHDL module to receive data after 2 clock cycles of conversion start (as refer to datasheet) .

However, there is around 2 clock cycle delay for the receiving process...maybe due to my counter/ loop process. Therefore the receiving process become inaccurate.

As busy signal is to tell device that data is ready and can receive data, is it better to use it as guideline for the receiving process?
Maybe due to inaccurate timing of receiving serial data with the clock cycle, i receive a few bits or sometime none of them from ADC.There is why i intent to use busy line.