uart verilog fsm help

[phobos1]

hi
i have problem with this uart fsm i'm not getting proper output at tx, i am using dcm to generate a 12 mhz clk for generating baud rates. i attached my code below:




module TX_fsm(
input clk,
input rst,
input baudclk,
input go,
input [7:0] data,
output reg TX,
output reg FIN
);

wire cclk;

BUFG UUT4 (.I(clk),.O(cclk));

parameter IDLE = 4'b0000,
START = 4'b0001,
BUSY = 4'b0010,
STOP1 = 4'b0011,
STOP2 = 4'b0100,
DONE = 4'b0101;


reg [3:0]state, next;
reg [7:0]temp,temp_reg;
reg [3:0]i,i_reg;


always@(posedge cclk, posedge rst)
begin
if (rst)
begin
state <= IDLE;
temp <= 8'd0;
i <= 4'd0;
end
else
begin
state <= next;
temp <= temp_reg;
i <= i_reg;
end
end

always@*
begin
TX = 1'b0;
FIN = 1'b0;
next = 4'bx;
temp_reg = 8'd0;
i_reg = 4'd0;
case (state)
IDLE : begin
TX = 1'b1;
if (!go)
next = IDLE;
else
next = START;
end
START : begin
FIN = 1'b0;
TX = 1'b0;
if (baudclk)
begin
temp_reg[7:0] = data[7:0];
next = BUSY;
end
end
BUSY : begin
TX = temp[7-i];
if (baudclk)
i_reg = i[3:0] + 1'b1;
if (i[3:0] > 4'd7)
next = STOP1;
else
next = BUSY;
end
STOP1 : begin
TX = 1'b1;
if (baudclk)
begin
next = STOP2;
i_reg = 4'd0;
end
end
STOP2 : begin
TX = 1'b1;
if (baudclk)
next = DONE;
end
DONE : begin
TX = 1'b1;
next = IDLE;
FIN = 1'b1;
end
endcase
end
endmodule

 

[FvM]

i am using dcm to generate a 12 mhz clk for generating baud rates.

The relation between clk and baudclk is unclear. The code can only work, if baudclk is generated as a clock enable, active for one cycle of clk, and with correct timing related to clk.

 

[phobos1]

module TX_fsm(
input clk,
input rst,
input go,
input [7:0] data,
output reg TX,
output reg FIN,
output [16:0]b
);

wire cclk;

// clock buffer
IBUFG UUT4 (.I(clk),.O(cclk));


parameter IDLE = 4'b0000,
START = 4'b0001,
BUSY = 4'b0010,
STOP1 = 4'b0011,
STOP2 = 4'b0100,
DONE = 4'b0101;


reg [3:0]state, next;
reg [7:0]temp,temp_reg;
reg [3:0]i,i_reg;
reg [16:0]breg,b;

always@(posedge cclk, posedge rst)
begin
if (rst)
begin
state <= IDLE;
temp <= 8'd0;
i <= 4'd0;
b <= 17'd0;
end
else
begin
state <= next;
temp <= temp_reg;
i <= i_reg;
b <= breg;
end
end

always@*
begin
TX = 1'b0;
FIN = 1'b0;
next = 4'bx;
temp_reg = 8'd0;
i_reg = 4'd0;
case (state)
IDLE : begin
TX = 1'b1;
if (!go)
next = IDLE;
else
next = START;
end
START : begin
FIN = 1'b0;
TX = 1'b0;
if (b == 17'd434)
begin
temp_reg[7:0] = data[7:0];
breg = 17'd0;
next = BUSY;
end
else
breg = b + 1'b1;
end
BUSY : begin
TX = temp[7-i];
if (b == 17'd434)
begin
i_reg = i[3:0] + 1'b1;
breg = 17'd0;
if (i[3:0] > 4'd7)
next = STOP1;
else
next = BUSY;
end
else
breg = b + 1'b1;
end
STOP1 : begin
TX = 1'b1;
if (b == 17'd434)
begin
i_reg = 4'd0;
breg = 17'd0;
next = STOP2;
end
else
breg = b + 1'b1;
end
STOP2 : begin
TX = 1'b1;
if (b == 17'd434)
begin
breg = 17'd0;
next = DONE;
end
else
breg = b + 1'b1;
end
DONE : begin
TX = 1'b1;
next = IDLE;
FIN = 1'b1;
end
endcase
end
endmodule

is this ok for 50 mhz with 115200 baudrate

 

[mrflibble]

is this ok for 50 mhz with 115200 baudrate

is that a question or a statement