library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
entity tx is
port
(
clk: in std_logic;
reset: in std_logic;
data: in std_logic_vector( 7 downto 0);
flag: out std_logic;
transmit: out std_logic);
end tx;
architecture modul of tx is
signal counter: integer range 0 to 5209:=0;
signal index : integer range 0 to 7:=0;
signal b_data : std_logic_vector( 7 downto 0):="00000000";
signal b_transmit: std_logic:='1';
signal b_flag: std_logic:='0';
type state_m is(IDLE, START, D0,D1,D2,D3,D4,D5,D6,D7, STOP1,STOP2,SecureDelay);
signal state_new: state_m :=IDLE;
begin
transmit <= b_transmit;
flag <= b_flag;
process(clk,reset)
begin
if (reset='1') then
counter<=0;
index<=0;
b_transmit<='1';
b_flag<='0';
b_data<="00000000";
state_new<=IDLE;
elsif rising_edge(clk) then
case state_new is
--------------------------------------
when IDLE=>
b_transmit<='1';
index<=0;
counter<=0;
if(b_flag<='0') then
b_data<=data;
b_flag<='1';
state_new<=START;
end if;
--------------------------------------
when START=>
b_transmit<='0';
if counter=5208 then
counter<=0;
state_new<=D0;
else counter<= counter+1;
end if;
--------------------------------------
when D0=>
b_transmit<=b_data(0);
if counter=5208 then
counter<=0;
state_new<=D1;
else counter<= counter+1;
end if;
--------------------------------------
when D1=>
b_transmit<=b_data(1);
if counter=5208 then
counter<=0;
state_new<=D2;
else counter<= counter+1;
end if;
--------------------------------------
when D2=>
b_transmit<=b_data(2);
if counter=5208 then
counter<=0;
state_new<=D3;
else counter<= counter+1;
end if;
--------------------------------------
when D3=>
b_transmit<=b_data(3);
if counter=5208 then
counter<=0;
state_new<=D4;
else counter<= counter+1;
end if;
--------------------------------------
when D4=>
b_transmit<=b_data(4);
if counter=5208 then
counter<=0;
state_new<=D5;
else counter<= counter+1;
end if;
--------------------------------------
when D5=>
b_transmit<=b_data(5);
if counter=5208 then
counter<=0;
state_new<=D6;
else counter<= counter+1;
end if;
--------------------------------------
when D6=>
b_transmit<=b_data(6);
if counter=5208 then
counter<=0;
state_new<=D7;
else counter<= counter+1;
end if;
--------------------------------------
when D7=>
b_transmit<=b_data(7);
if counter=5208 then
counter<=0;
state_new<=STOP1;
else counter<= counter+1;
end if;
--------------------------------------
when STOP1=>
b_transmit<='1';
if counter=5208 then
counter<=0;
state_new<=STOP2;
else counter<= counter+1;
end if;
--------------------------------------
when STOP2=>
b_transmit<='1';
if counter=2604 then
counter<=0;
state_new<=SecureDelay;
else counter<= counter+1;
end if;
--------------------------------------
When SecureDelay=>
b_transmit<='1';
if counter=5208 then
counter<=0;
b_flag<='0';
state_new<=IDLE;
else counter<= counter+1;
end if;
end case;
end if;
end process;
end modul;