UART timing issues in Verilog HDL

[vickyuet]

Dear all,

I am trying to design a UART in verilog HDL but i got some questions left unanswered yet?

1-how we design uart clock from system clock according to different baud rates???? say if i choose a specific baud rate 9600 what are the timing parameters that i had to kept in mind and how i calculate it.
2-say if i want to design programmable timing for different range of baud rates what modifications i had to do?
3-Receiver:
in receiver how to sample it at the middle of bit period,

Can any one help me or give me some good reference where these are addressed in detail...

regards.

 

[kirill]

will be your design connected to PC?

 

[std_match]

Most commercial UART's seem to use a clock 16 times the baud rate.
They detect the leading edge of the start bit and then they sample in the middle of all bits (including the start bit) just by counting clock cycles.
Each sampling is normally done by 3 consecutive sub-samples with a majority voting. If the start bit is sampled as '1' it is a false start bit error.
If the stop bit is sampled as '0' it is a framing error.

If you design your own UART you don't have to do it this way.
If you skip the majority sampling you can have a working UART with a clock frequency as low as 3 times the baud rate.

 

[vickyuet]

yes it is connected through hyper terminal??