library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity test is
port(
start : in std_logic;
clk: in std_logic;
rslt: out std_logic);
end test;
architecture davranis of test is
COMPONENT uart_tx
PORT(
clk: in std_logic;
reset: in std_logic;
inpt : in std_logic_vector(7 downto 0);
send: in std_logic;
ok: out std_logic;
rslt: out std_logic);
END COMPONENT;
type d_type is array (0 to 15) of std_logic_vector(7 downto 0);
constant data1: d_type:=(x"22",x"53",x"45",x"4c",x"41",x"4D",x"20",x"46",x"50",x"47",x"41",x"22",x"00",x"00",x"00",x"00");
signal counter : std_logic_vector(3 downto 0):=(others=>'0');
signal counter_next : std_logic_vector(3 downto 0):=(others=>'0');
signal active : std_logic;
signal ok : std_logic;
signal inpt : std_logic_vector(7 downto 0);
begin
Inst_uart_tx : uart_tx PORT MAP (clk=>clk,reset=>'0',inpt=>inpt,send=>active, ok=>ok,rslt=>rslt);
process(clk)
begin
if rising_edge(clk) then
counter<=counter_next;
end if;
end process;
active<='1' when start='1' and counter <"1101" else '0';
counter_next<=counter+1 when ok='1' else counter;
inpt<=data1(conv_integer(counter));
end davranis;