Pravinspidy
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Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 component uart_transceiver is port( sys_rst: in std_logic; sys_clk: in std_logic; uart_rx : in std_logic; uart_tx : out std_logic; divisor : in std_logic_vector(15 downto 0); rx_data : out std_logic_vector(7 downto 0); rx_done: out std_logic; rx_bsy: out std_logic; tx_data : in std_logic_vector(7 downto 0); tx_wr : in std_logic; tx_done: out std_logic ); end component;
To use that UART you must declare a component in your module:
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 component uart_transceiver is port( sys_rst: in std_logic; sys_clk: in std_logic; uart_rx : in std_logic; uart_tx : out std_logic; divisor : in std_logic_vector(15 downto 0); rx_data : out std_logic_vector(7 downto 0); rx_done: out std_logic; rx_bsy: out std_logic; tx_data : in std_logic_vector(7 downto 0); tx_wr : in std_logic; tx_done: out std_logic ); end component;
The interface is pretty obvious except for divisor. It's a parameter of a baud rate generator, and it's not documented, so I had to guess. For 115 200 baud and 50 MHz clock it's x"001B".
Actually, it's clk frequency / 16 / desired baud rate (rounded to nearest integer, I guess).For 115 200 baud and 50 MHz clock it's x"001B".
What code would yo like to see, specifically? Port map, or something else? I'm not sure my code will help you much...hi, thanks a lot can u give the full code for this so that i can understand easily..........
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity RS232_test is Port ( clk_50MHz : in STD_LOGIC; rst : in STD_LOGIC; RS232_rx : in STD_LOGIC; RS232_tx : out STD_LOGIC; LED : out STD_LOGIC_VECTOR (7 downto 0)); end RS232_test; architecture Behavioral of RS232_test is component uart_transceiver is port( sys_rst: in std_logic; sys_clk: in std_logic; uart_rx : in std_logic; uart_tx : out std_logic; divisor : in std_logic_vector(15 downto 0); rx_data : out std_logic_vector(7 downto 0); rx_done: out std_logic; rx_bsy: out std_logic; tx_data : in std_logic_vector(7 downto 0); tx_wr : in std_logic; tx_done: out std_logic ); end component; signal RXByte,TXByte, debug: std_logic_vector(7 downto 0); signal tx_req: std_logic; signal tx_end: std_logic; signal rx_ready,rx_busy: std_logic; type stateType is (receiving, transmitting); signal state: stateType; begin RS232: uart_transceiver port map ( sys_rst => rst, sys_clk => clk_50MHZ, uart_rx => RS232_rx, uart_tx => RS232_tx, divisor => x"001B", rx_data => RXByte, rx_done => rx_ready, rx_bsy => rx_busy, tx_data => TXByte, tx_wr => tx_req, tx_done => tx_end ); Mirror: process (clk_50MHz, rst) begin if rst = '1' then TXByte <= x"01"; state <= receiving; tx_req <= '0'; elsif rising_edge(clk_50MHz) then case state is when receiving => if rx_ready = '1' then state <= transmitting; TXByte <= RXByte; LED <= RXByte; tx_req <= '1'; end if; when transmitting => tx_req <= '0'; if tx_end = '1' then state <= receiving; end if; end case; end if; end process; end architecture;
can u plz post the complete code with test benchTo use that UART you must declare a component in your module:
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 component uart_transceiver is port( sys_rst: in std_logic; sys_clk: in std_logic; uart_rx : in std_logic; uart_tx : out std_logic; divisor : in std_logic_vector(15 downto 0); rx_data : out std_logic_vector(7 downto 0); rx_done: out std_logic; rx_bsy: out std_logic; tx_data : in std_logic_vector(7 downto 0); tx_wr : in std_logic; tx_done: out std_logic ); end component;
The interface is pretty obvious except for divisor. It's a parameter of a baud rate generator, and it's not documented, so I had to guess. For 115 200 baud and 50 MHz clock it's x"001B".
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