UART 16550 FIFO problem

[addn]

Hi,everybody

what does UART 16550 FIFO structure use??

synchronous or asynchronous

thanks

 

[Nimer]

hi

i dont understand the question .. from what i know the fifo structre is synch . but you conrol the synch signals ...see the data sheet for the right answer .

regards

 

[pahol]

Please give more information in your question.
UART is async, most of FIFO is sync.

 

[addn]

hi,

about asyn and syn FIFO,please refer to following link

h**p://direct.xilinx.com/bvdocs/appnotes/xapp051.pdf

my question is that

according to 16550 datasheet

the parameter of RC(read cycle) and WC(write cycle) are 280 ns

if 16550 use 1.8432 M Hz as system clock and syn FIFO

then we can find out that the syn FIFO's speed can't to match RC and WC

 

[sheik_vb]

Hi,
u can use the sync fifo, but u need double-buffer the signal.