What is the interconnect's parasitic resistance and capacitance range (min. and max. values) for a typical VLSI process (or for a spesific process) ? Could anyone give some info or recommend a source that I can find info on this question?
It is dependent on technology node. For typical 180nm technology node, resistance is of the order of 60 ohms, ground and coupling capacitance of 200fF and inductance of 4nH for a typical interconnect length of 2.5mm. These data's are not direct from foundry. Using predictive models, we can found the parasitic values.