Your collector is substrate, your base is well, your emitter is
S/D. This is a very normal CMOS situation and the only vertical
BJT in many flows, hence the only device with decently high
areal current density. It can unfortunately not serve all roles
since one terminal is pinned.
Your other diode is the N-well, P S/D "diode" which is in fact
the E-B of that PNP, so you have to be aware / sure about
what that action will be, when you consider what the "diode"
will do. It could help, or it could hurt.
It is very helpful to draw cutaway figures of the I/O devices
and ESD elements, if you have an eye for device structure
you would immediately recognize the PNP in a PMOS FET.
Less obvious are the combinations of lateral and vertical
features that make (low quality, but still troublesome)
SCRs and lateral BJTs.
I hate JI technologies myself. Not the transistors so much.
It's the in-laws.