praveen450
Member level 5
- Joined
- May 13, 2011
- Messages
- 89
- Helped
- 0
- Reputation
- 0
- Reaction score
- 0
- Trophy points
- 1,286
- Activity points
- 1,957
Hi,
I designed a two stage with two supply voltges and the simulations are working fine for DC.
When I'm measuring the results on physical chip for DC, I'm seeing the following observations:
1) When supply voltages are increased from 0 to Vdd1 nd Vdd2, the currents drawn by the PA are zero (good)
2) When I'm increasing the first stage bias voltage from 0 to vbias1 with second stage bias voltage at 0V. The first stage is drawing current and second stage is not drawing any current (good). I have done the same procedure for second by keeping first stage bias voltage at 0 and changing second stage bias from 0 to vbias2. The first stage is not drawing any current.
3) Now wjen I bias the second stage at vbias2 and slowly increasing the bias of vbias1, I'm seeing decreasein current in second stage even the vbias2 remains unchanged.
Could anyone possibly explain why this is happening?.
I ran the simulations in cadence and it is working fine. Both the stages are independent for DC testing in simulations.
Thanks in advance
I designed a two stage with two supply voltges and the simulations are working fine for DC.
When I'm measuring the results on physical chip for DC, I'm seeing the following observations:
1) When supply voltages are increased from 0 to Vdd1 nd Vdd2, the currents drawn by the PA are zero (good)
2) When I'm increasing the first stage bias voltage from 0 to vbias1 with second stage bias voltage at 0V. The first stage is drawing current and second stage is not drawing any current (good). I have done the same procedure for second by keeping first stage bias voltage at 0 and changing second stage bias from 0 to vbias2. The first stage is not drawing any current.
3) Now wjen I bias the second stage at vbias2 and slowly increasing the bias of vbias1, I'm seeing decreasein current in second stage even the vbias2 remains unchanged.
Could anyone possibly explain why this is happening?.
I ran the simulations in cadence and it is working fine. Both the stages are independent for DC testing in simulations.
Thanks in advance