I met two problems about the DRC in cadence.
1. I draw some simple circuit that only two metal lines is on the graph, but when I run DRC, it failed. the the log message tole me that "rcxtoDFII fork terminated abnormally"
2. When DRC is run for some more complex circuit , the message "failed to build VDB. Cannot submit DRC RUN" appeared.
Hi,
What DRC tool you use?
Diva, Assura, Dracula? (these come with Cadence) Or other external tool like Calibre or Hercules?
The message rcx.... can mean something else depending of tools....and also VDB.
I met two problems about the DRC in cadence.
1. I draw some simple circuit that only two metal lines is on the graph, but when I run DRC, it failed. the the log message tole me that "rcxtoDFII fork terminated abnormally"
2. When DRC is run for some more complex circuit , the message "failed to build VDB. Cannot submit DRC RUN" appeared.
Could anyone give me any guidance? Thanks!
No 2. Failed to run VDB.
This usually occurs if you are RE running a failed run. There is normally a few hidden assura file you need to delete to restart a clean run. drc.Last.state.
One common reason for this problem happens when your circuit using Place-and-Route tool whose DBUPerUU s different to the one in Cadence. Look into this, otherwise, put three lines above and below that error statement.
Q.1 : Get more info .... like post the log file... I think I can definitely look into these.
Hi, this is praveen. I am also having the same problem. I think i didnt setup the UMC libraries properly. Can anyone help me how to setup the UMC018 into the assura in CADENCE.
If you are using Assura Tools (for DRC) with diva rules then you will get this problem. Try running drc using diva from the menu option Verify ----> DRC.
I had this problem recently when there was a block with a wrong path was existing on the layout. It was so small that I couldn't find it easily. I suggest you also to check if you have some wrong components on the layout. Then, you need to remove all the log files related to drc. Some will be hidden, so best is to check with ls -la. After, removing them restarting cadence helped in my case.
hi i have the same problem of VDB. Can someone plz let me know how to delete the last drc state? Also in the last post what do you mean by a coponent with the wrong path? I am not using nested layoute.g calling any other layout in a new one. Do you mean if I have two same resistor instances of same values I might have interchanged them.?
The problem of Failed to build VDB usually comes when you dont include all the switches during the DRC run. I use DRC from Assura and to run that I use the following switches:
1)Ext_Latchup
2)GridCheck
3)BEOL Stack323( Depending upon the thin and thick metals that I use)
I hope setting this switch configuration may help.