albbg or std_matchThe short answer is "yes", you must treat them as asynchronous.
With dividers, it is possible to generate more than one clock from one PLL so they can be treated as having synchronized edges.
This is OK since the PLL jitter will not influence the relationship between the different clocks.
If the clocks are generated from different PLL's, the jitter can affect in opposite directions and create problems. The data path delay between registers must be longer than twice the maximum PLL jitter if you want to treat them as synchronous. That is probably a bad idea but not impossible. The long term drift will be zero, so a simple FIFO can be used to transfer data between the clock domains. That is called a "jitter buffer".
For digital design, "asynchronous" means that you can't freely pass signals between the clock domains.
In this case, the clocks will be "phase locked" to each other. This is "synchronous" in some sense, but they will have independent jitter. This will probably make it impossible to pass signals between the clock domains without a synchronization mechanism.
In other words, you should treat the clocks as asynchronous.
One possible way around this is to phase shift one of the clocks, so that they don't have simultaneous edges. The downside is that fMax will be reduced.
SunnySkyguyIF both PLL's are synchronous to the Cystal, then they will be synchronous to each other.
Strictly speaking two clocks are synchronous each other if the edges are aligned, so to have the same frequency (isofrequency) is not enough. If the edges are almost aligned then they are pleysiochronous.IF both PLL's are synchronous to the Cystal, then they will be synchronous to each other.
THe awssumption is two PLL with different output frequencies, f1,f2 with a common ref freq from a crystal, f0Since f1 =x1/y1 *f0 and f2 = x2/y2 *f0 when x,y are mulitpler & divider integersSynchronous behavior of f1 and f2 are said to be locked to each other due to a common harmonic of each that matches or a common sub harmonic that matches.One simple example is two power utilities are locked to the international Cesium clock divided down to 50 Hz and 60Hz.Since 1 second or 1Hz is one subharmonic common to both they are said to be synchronous to each other by some ratio of integers.Suppose there are two PLLs and both of them using the same crystal. Will the clocks from both of the PLLs be treated as asynchronous?Regards