Two PLL using same crystal

[sun_ray]

Suppose there are two PLLs and both of them using the same crystal. Will the clocks from both of the PLLs be treated as asynchronous?

Regards

 

[albbg]

They will have the same output frequency but, in general, different phases.

 

[std_match]

The short answer is "yes", you must treat them as asynchronous.

With dividers, it is possible to generate more than one clock from one PLL so they can be treated as having synchronized edges.
This is OK since the PLL jitter will not influence the relationship between the different clocks.

If the clocks are generated from different PLL's, the jitter can affect in opposite directions and create problems. The data path delay between registers must be longer than twice the maximum PLL jitter if you want to treat them as synchronous. That is probably a bad idea but not impossible. The long term drift will be zero, so a simple FIFO can be used to transfer data between the clock domains. That is called a "jitter buffer".

 

[sun_ray]

The short answer is "yes", you must treat them as asynchronous.

With dividers, it is possible to generate more than one clock from one PLL so they can be treated as having synchronized edges.
This is OK since the PLL jitter will not influence the relationship between the different clocks.

If the clocks are generated from different PLL's, the jitter can affect in opposite directions and create problems. The data path delay between registers must be longer than twice the maximum PLL jitter if you want to treat them as synchronous. That is probably a bad idea but not impossible. The long term drift will be zero, so a simple FIFO can be used to transfer data between the clock domains. That is called a "jitter buffer".

albbg or std_match

The two PLLs if was using different crystals to generate the clocks, or to state in other way, if each one of the two PLLs has their own crystals, then the clocks from the two PLLs would have been asynchronous. But here both the PLLs are using the same crystal. Will not then the clocks be synchronous from both the PLLs in this case? Why will not be synchronous in this case if you are still saying it will be asynchronous?

Thanks for the replies.

Regards

 

[std_match]

For digital design, "asynchronous" means that you can't freely pass signals between the clock domains.
In this case, the clocks will be "phase locked" to each other. This is "synchronous" in some sense, but they will have independent jitter. This will probably make it impossible to pass signals between the clock domains without a synchronization mechanism.
In other words, you should treat the clocks as asynchronous.

One possible way around this is to phase shift one of the clocks, so that they don't have simultaneous edges. The downside is that fMax will be reduced.

 

[sun_ray]

For digital design, "asynchronous" means that you can't freely pass signals between the clock domains.
In this case, the clocks will be "phase locked" to each other. This is "synchronous" in some sense, but they will have independent jitter. This will probably make it impossible to pass signals between the clock domains without a synchronization mechanism.
In other words, you should treat the clocks as asynchronous.

One possible way around this is to phase shift one of the clocks, so that they don't have simultaneous edges. The downside is that fMax will be reduced.

std_match or anybody

Let us provide another question as below.

The two PLLs are using different crystals to generate the clocks, or to state in other way, each one of the two PLLs have their own crystals. What will be the difference between the asynchronous nature of clocks from both the PLLs in this case with the asynchronous nature of the clocks from both the PLLs in the earlier case?

Thank you for the reply.

Regards

 

[std_match]

If each PLL has it's own crystal, the clocks must be treated as asynchronous. No workaround is possible. The phase relationship between the clocks is unknown. and will change.
As I mentioned earlier, with one crystal the PLL's will be phase locked to each other.

 

[D.A.(Tony)Stewart]

IF both PLL's are synchronous to the Cystal, then they will be synchronous to each other.

 

[sun_ray]

IF both PLL's are synchronous to the Cystal, then they will be synchronous to each other.

SunnySkyguy

What do you mean by both PLLs are synchronous to the crystal?

What are the conditions, when more than one PLL be synchronous to one crystal if more than one PLL are using one crystal?

Why will the clocks from both PLLs be synchronous to each other if the PLLs are synchronous to the crystal?

 

[albbg]

IF both PLL's are synchronous to the Cystal, then they will be synchronous to each other.

Strictly speaking two clocks are synchronous each other if the edges are aligned, so to have the same frequency (isofrequency) is not enough. If the edges are almost aligned then they are pleysiochronous.
In this case, since you cannot control the pahse of the reference arriving on each PLL you will have two isofreqeuncy but not synchronous clocks.
However, sun_ray, what's the use of these two clocks in your application ?

 

[D.A.(Tony)Stewart]

plesiochronous (meaning almost) in the Telecom world I am familiar with applies to pseudo-synchronous with offset frequencies and thus drifting phases synchronized by bit shift or missing and extra pulses. of a higher clock.

Synchronous does NOT have to be phase synchronous by its familiar use, however in PLL's one source must be mixed to measure phase error and result in 0 90 or 180 deg offset as there are many types of mixers and not all are 0 deg offset.

Thus there must be one common harmonic or subharmonic where the 3 signals have the same value. Phase is irrelevant.

Consider a scope trigger. You achieve a steady signal on the display whenever the trigger is synchronized to the incoming signal or any harmonic of the sweep rate.

Phase difference only shifts the steady image

Therefore I stand by my original statement.

If you want to add the adjective "Phase" to Synchronous then that implies it is also frequency synchronous AND Phase sync'd with a known offset.

 

[albbg]

SunnySkyguy, I think we do not agree just on the definitions (probably about the term "plesiochronous" you are rigth). Your examples are clear.
Then you are saying that the terms isofrequency and synchronous are synonyms. Isn't it ?

 

[D.A.(Tony)Stewart]

I have never used the term "isofrequency" in 35 yrs as an R&D /Test Engineer, but I see it means same f, which is a vague definition.

In the world of Time and Frequency Synch. There is no requirement that all clocks must be the same frequency to be in sync. It just requires a common denominator to be in sync.

When I designed a VLF Doppler Navigation 5ch Rx in 1975, I used 100 Hz as the PLL to sync with 16.4kHz, 17.4, 21.x which were all US NAvy transmitters sync'd to a Cesium global clock at a much higher f.


the stability was 1e-10 on short term and diurnal shift during sunset /sunrise would cause some phase shift. We used it to track an automated custom weather station with a Tx to GOES 1 from a floating ice flow in the Beaufort Sea to track ice flows that threatened to shear oil rigs.


See my point yet?

 

[biff44]

plesiochronous (meaning almost) in the Telecom world I am familiar with applies to pseudo-synchronous with offset frequencies and thus drifting phases synchronized by bit shift or missing and extra pulses. of a higher clock.
.

I agree, they are "somewhat" synchronous.

If you have two PLL's, you probably have them set to different output frequencies. so right away you have to question how two very different frequencies can be "correlated" to each other.

Further, since many modern PLLs are "fractional" there is also a rotating phase term, or slow speed phase walk, going on to achieve that "fractionality".

Finally, the divider in a PLL works oddly, if it is a divide by 1000, for instance, after 1000 input pulses, it outputs one output pulse. So what happens if they power supply in PLL1 comes up a little quicker than that in PLL2? Well, PLL1 counts additional input pulses before the PLL2 counter even starts. So there is a fixed phase difference between the two PLL outputs. Only with some really careful startup circuitry can you get them both synchronized.

What ARE they synchronous on? Well, the phase noise of PLL1 will be correlated to that of PLL2. Some systems actually use this as part of the system design. Also, the frequency drift will be the same...i.e. if PLL1 is 10ppm high, so will PLL2.

 

[D.A.(Tony)Stewart]

Two PLL's sync'd to common source with ALWAYS be Synchronous limited by the tolerance of each. The sync error result is the sum of all f errors in PPM, which includes, dividers, multipliers, missing/extra bit resolution and fractional N types.

Again the common denominator frequency is where you can measure the resulting Sync error or using a precision counter, mathematically deduce the sync error with a frequency reference such as GPS, WWVB or equiv.

For example, at one time 60 Hz major suppliers were Cesium time sync's and now with global power sharing, frequency and phase are correction factors to adjust power delivery from host to shared targets with a regional regulator in charge of defining F stability overall.

 

[sun_ray]

SunnySkyguy

Can you please answer our questions in our last post? The answer to our question lost due to a long discussion after our last post.

Regards

 

[albbg]

sun_ray, is your question just a theoretical one or have you a specific application these two clocks are used for ? In this last case could you explain which one ?

 

[D.A.(Tony)Stewart]

Suppose there are two PLLs and both of them using the same crystal. Will the clocks from both of the PLLs be treated as asynchronous?Regards

THe awssumption is two PLL with different output frequencies, f1,f2 with a common ref freq from a crystal, f0Since f1 =x1/y1 *f0 and f2 = x2/y2 *f0 when x,y are mulitpler & divider integersSynchronous behavior of f1 and f2 are said to be locked to each other due to a common harmonic of each that matches or a common sub harmonic that matches.One simple example is two power utilities are locked to the international Cesium clock divided down to 50 Hz and 60Hz.Since 1 second or 1Hz is one subharmonic common to both they are said to be synchronous to each other by some ratio of integers.