Thanks my friends,
Is there another advantage of the second configuration to convince me to adopt it ?
That Is really a challenge for me. In fact the figure 1 has the advantage to have a small area (around 75%) compared to the 2nd.
referring to the interconnect parasitics . you cannot reduce the gate capacitance of the next state and diffusion capacitance which are seen as the load.
I will go to no.1.
The size of the delay cell each shouldn't be very big. So don't need to worry about the long wire from cell1 to cell3 at all. Also the layout can look more neat.