We have One Flip flop with Clock(Clk1) and another Flip flop with Clk2) now data is passing from one Flip flop to another i.e., ff1 to ff2
If clk1>clk2 then there is chance of data getting lost
If clk<clk2 then my data will be repeating.
so wht shud be ideal soln ?? clk1 n clk2 can be any frequency !!
Shiv your requirements are too vague. The solution provided is also vague and incomplete until the specifications are fully understood. In general, when we try and interface signals between two clock domain there are three possible ways to do it correctly:
1. have synchronizers to take care of metastability issue (a pair/triplet of flops in series clocked with receiving clocks)
2. replace the protocol with req/ack protocol to ensure you've sampled it only as much as the design requires
3. asynch fifos when the number of signals to be transmitted is a large group of similar data wires
do you understand why we shouldn't directly interface two flops clocked with different clocks and start using the data at the output of the second flop?
do you understand why we shouldn't directly interface two flops clocked with different clocks and start using the data at the output of the second flop?
Switching of a signal in clock domain A may seem to be asynchronous at the input of the flop clocked by clock B. This may potentially violate both setup and hold time of the second flop resulting in a metastable state of the sequential node
If the two clocks are relative i.e clock1 = 1/2clock2 or 1/4clock2 or 1/8clock2 then handshaking can be used or else there needs to be much control on the handshaking using some metastable flip flops.