hithesh123
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I have a 4bit counter in my vhdl code. when the count<8, I load data to a MS 8-bits of a registers and when the count>8, I load data to LS 8-bits of the register.
In the synthesis report, why are 2 5-bit comparators inferred - one for less than and the other for greater/equal.
In the synthesis report, why are 2 5-bit comparators inferred - one for less than and the other for greater/equal.