two clock, how to find out which frequency is higher?

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two clock,one is clocka, the other is clockb
i don't know the frequency of them
if the frequency of clocka is higher than that of clockb, output is '1'
how to implement it in verilog?
 

count the rising edges of each clock. First to reach a preset count is highest frequency.
There may be other ways, but that should work, and if you know the basics of verilog it should be easy to code.
 

is register output or combination output?
if register output,which clock should i choose?
if combination output, it have glitch
 

Hi... think my solution could be simple... have a n-bit counter for both the clocks...start the both the counters at the same time... whenever overflow occurs in any one of the counter reset both the counters... the colck which leads to overflow is the fastest...this overflow could be used to set a flip-flop so that the faster clock will be known until another overflow occurs...
 

Nice idea lordsathish,
But dont you think ths solution is a lot area consuming solution ?
 

master_picengineer said:
Nice idea lordsathish,
But dont you think ths solution is a lot area consuming solution ?
Click to expand...

is there a better way which consumes lesser area...?
 

the simplest methode is the using of the phase detector
 

create 2 counter, let the counter count until 10(or some number but must larger than 2 because 2 clock may not triger at the same time) and then compare the 2 counters output value to determine which 1 is larger .

if (clka'event and clka = 1) then
cntra <= cntra + 1;
end if;

if (clkb'event and clkb =1) then
cntrb <= cntrb +1;
end if;

if (cntra == 10 and cntra < cntrb) then
output <= 1;
// reset cntr logic
end if;
 

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