littlefield
Junior Member level 3
two clock,one is clocka, the other is clockb
i don't know the frequency of them
if the frequency of clocka is higher than that of clockb, output is '1'
how to implement it in verilog?
i don't know the frequency of them
if the frequency of clocka is higher than that of clockb, output is '1'
how to implement it in verilog?