Well, I suggest that if you could have a control like "HOLD" or "RDY" at the 1MHz data transmitter unit, then you don't might need the FIFO build ups, infact a couple of registers\buffers do the job the best and I have already done it even under async clock devices....However using FIFO logic increases your future expansion, say you can connect even high speed devices with just HOLD or RDY controls....UP Conversion or DOWN conversion is not a big issue unless you have a master as your tx or Rx device...If u need more info,describe your critical part and let's see what v could do...
Regards