triplewell
In general MOS devices have 4 terminals D G S B.
B terminal [Bulk/Substrate] has an important role in MOS functionality. From the back-side of a MOS the substrate potential can affect the channel characteristics - it resembles very similar functionality of a Gate terminal of a FET [not a MOSFET but, a Field Effect Transistor], it is called back-gate. You want finer control of the back-gate - go get a triple-well MOS.
We call them isolated-MOS too - the reason being - electrically isolating the bulk node from global substrates.
Although it is not mandatory to keep Source & Substrate connection of a MOS be shorted together, there are design requirements, where the S,B needs to be locally shorted - please note, I did not mention yet - S,B shorted to VDD or GND. Keep it at whatever different potential from global VDD/VSS you need a triple-well process.
Triple well further reduces signal and noise coupling to and from substrate [OK, same as noise isolation].
Triple well might help addressing different potential requirements at IO ESD regions.
Well, somewhere I might have read something about virtual power switching [power-gating] using back-gate [not sure].
All such things are possible by using triple well structures.