tenso
Advanced Member level 4
TSMC's 65nm process comes in two flavors for mixed signal and RF design, general purpose and low power. On CMC's website it says that the low power has vdd of 1.2V/2.5V
https://www.cmc.ca/WhatWeOffer/Products/CMC-00131-53461.aspx
and the general purpose has a vdd of 1V/2.5V.
https://www.cmc.ca/WhatWeOffer/Products/CMC-00200-01409.aspx
so my questions are (and they might be stupid ones)
- Why is the vdd higher for the low power version ( 1.2 V) versus the general purpose version ( 1 V)?
- What is the difference between the core voltage and the I/O voltage ( which is 2.5V for both? Are we talking about the supply voltages for the transistors connected to the bond pads?
https://www.cmc.ca/WhatWeOffer/Products/CMC-00131-53461.aspx
and the general purpose has a vdd of 1V/2.5V.
https://www.cmc.ca/WhatWeOffer/Products/CMC-00200-01409.aspx
so my questions are (and they might be stupid ones)
- Why is the vdd higher for the low power version ( 1.2 V) versus the general purpose version ( 1 V)?
- What is the difference between the core voltage and the I/O voltage ( which is 2.5V for both? Are we talking about the supply voltages for the transistors connected to the bond pads?
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