TSMC 0.18 RF designkit for ADS2005A

[shilong_xu]

tsmc s12

Hi everyone.

I've installed the TSMC CMOS 0.18um 2.0v design kit on my ADS 2005A software

whenever I use one of the TSMC component for the simplest simulation ( for example, S-Parameters of R-C network) the simulator gives me this known error:

"R1 is an instance of on undefined model 'TSMC_CM018RF_BB_SUBCKT_mpo1' "


does anyone familiar with this problem? could some one help me please? this
Thanks

 

[Grig]

Hi
Can You e-mail me your deskit? - I can try repair it

 

[shilong_xu]

ok, I attach the designkit here, thanks alot

 

[hanm]

Hi.I think you didn't include the right model.

hanm

 

[ghostdaemon]

Hi everyone.

I've installed the TSMC CMOS 0.18um 2.0v design kit on my ADS 2005A software

whenever I use one of the TSMC component for the simplest simulation ( for example, S-Parameters of R-C network) the simulator gives me this known error:

"R1 is an instance of on undefined model 'TSMC_CM018RF_BB_SUBCKT_mpo1' "


does anyone familiar with this problem? could some one help me please? this
Thanks

please refer this topic:

Installation Instructions for the ADS Front End design kit for the TSMC 0.18um RF CMOS process from hxxp://www.tec.ufl.edu/~dojeda/intersil/report0723/david0723.html

 

[shilong_xu]

If it is the model problem, could someone offer the correct model.
I see the content of the *.net file, it is for Hspice. So when I make a schemetic simulation, in the schemetic, there are no model selection item at all, it is to say, the model does not installed successfully, could someone solve this problem??
thanks in advance

Added after 1 hours 41 minutes:

I have added the process model, but some error ocurs, like the "rn is a reserved sinature for noise... during parsing" why?
thanks

 

[serenade]

only I know is that 'rn' defind in file 'ResModel_dk.net' conflicts with ADS reserves.
but I do not know how to fix it. Are you sure this is the right designkit and it is for the version 2005A of ADS?

 

[shilong_xu]

yes,I am sure that it is the right PDK,but how to resolve this problems?

 

[mihiji]

ads error um~~

 

[Youncen]

You have to add the "technology include" which is a component in you tsmc componet panel，if it is not this stupid wrong，you can email me and offer some more information.

 

[Foufou]

Hi every bady,
I am a new searcher in RFIC and I would like to know how can we intall the 018TSMC design kit in ADS,
thinks
You can contact me by
travail_fay@yahoo.fr

 

[drabos]

you didn't use the substrate. (The proccess icon)

But if you use it, it will give you an other error message:-(

Added after 1 hours 43 minutes:

illegal subcircuit name: 'rn' is reserved for noise resistance.

BUt I can't find the 'rn' subcircuit

Added after 18 minutes:

The ResModel.net file define rn:

define rn ( n2 n1 body )


But, I feel, this isn't the answer for the question.

Added after 5 minutes:

So, if somebody knows the solution for this problem, please answer it!

 

[drabos]

Nobody knows the solution for this problem???

 

[drabos]

Any idea?

 

[khouly]

check this it is version 3

use the technology icon

khouly

 

[drabos]

The example project is working. So, it seems a good design kit!

Thank you!
You're a god, my friend!:-D

 

[khouly]

great , is there anyone have the 0.13 one

khouly

 

[drabos]

The RF transistors width is 2.5 um and I can't change that. What is the reason of it?
I can only change the nr.

Added after 18 minutes:

Has somebody an idea how can I simulate the gate-source capacitance of the transistor?

 

[khouly]

typically in RF CMSO model , the model is not a BSIM transistor alone but the transisitor is represented with
1) BSIM3v3 model
2) substarte network
3) gate network
4) source and drain diodes
it is called RF macro model of the MOS device

so modeling people efforts are very tough , so they model the transistor or specific W , and allow u to add multiple factor M , number of fingers ,

also don't forget , that u should refer to the layout manual of the technology to see the recommendation of the RF CMOS devices layout
like if hey take into account the the gate is double terminated or singal terminated , this effect a lot in the gate resistance


using S parameters u can get the input impdenace , the imaginary part is input capacitance of the MOS , but sure cgd will be effective as well


khouly

 

[drabos]

So, I just make an S parameter simulation???
But what should I use for termination?

Added after 17 minutes:

I should calculate the Zin from Γin?

Γin=S11+(S12*S21*Γl)/(1-S22*Γl)

Added after 31 minutes:

It would be a good solution if we can simulate the parasitic capacitances as Eldo, you can run an .OP simulation and all the datas are calculated.