#### vhdl34

##### Newbie level 6

Code:

```
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.all;
entity random is
port (
clkin : in std_logic;
random_num : out integer --output vector
);
end random;
architecture Behavioral of random is
begin
process(clkin)
variable rand_temp : std_logic_vector(9 downto 0):=( 9=> '1',others => '0');
variable temp : std_logic := '0';
variable rand: std_logic_vector(9 downto 0);
variable check : integer :=0;
variable state : std_logic := '0';
begin
if(rising_edge(clkin)) then
temp := rand_temp(9) xor rand_temp(8);
rand_temp(8 downto 0) := rand_temp(9 downto 1);
rand_temp(0) := temp;
if (rand_temp < "0010010001" )then
rand_temp := "0100011000";
end if;
if (rand_temp > "1100001010" )then
rand_temp := "0110010001";
end if;
check := to_integer(unsigned(rand_temp));
random_num <= check;
end if;
end process;
end Behavioral;
```