library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HundredusCounter is
Port( clk : in STD_LOGIC;
nCEN : out STD_LOGIC);
end HundredusCounter;
architecture Behavioral of HundredusCounter is
signal timer : STD_LOGIC_VECTOR(11 downto 0) := "000000000000";
signal reset: STD_LOGIC;
begin
process (clk, reset)
begin
if clk='1' and clk'event then
if reset = '1' then
timer <= timer + 1;
reset <= '0';
elsif timer = "111110100000" then --111110100000 means 4000
timer <= "000000000000";
reset <= '1';
else
timer <= timer + 1;
end if;
end if;
end process;
nCEN <= reset;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FreqCounter is
Port( rf_in : in STD_LOGIC;
rst : in STD_LOGIC;
freqOut : out STD_LOGIC_VECTOR(10 downto 0):= "00000000000");
end FreqCounter;
architecture Behavioral of FreqCounter is
signal counter : STD_LOGIC_VECTOR(10 downto 0) := "00000000000";
begin
process (rf_in, rst)
begin
if rst='1' then
counter <= "00000000000";
elsif rf_in='1' and rf_in'event then
counter <= counter + '1';
end if;
freqOut <= counter;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity d_latch_12_top is
Port ( EN : in STD_LOGIC;
D : in STD_LOGIC_VECTOR(10 downto 0);
Q : out STD_LOGIC_vector(10 downto 0));
end d_latch_12_top;
architecture Behavioral of d_latch_12_top is
begin
process (EN, D)
begin
if (EN = '1') then
Q <= D;
end if;
end process;
end Behavioral;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 -- sticking with your syncrhonous reset, though I'm not entirely sure what your original intention for reset was... proces (clk) begin if rising_edge(clk) then if (reset) then timer_1us <= (others => '0'); elsif (timer_1us < 3999) then -- use vhdl type conversion to make this integer of 3999 into a slv. timer_1us <= timer_1us +1; else timer_1us <= (others => '0'); end if; end if; end process;
Using a PLL is overly complicated in my opinion and I never suggested using one.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ENTITY edge_sync IS PORT ( clk : IN STD_LOGIC; ce : IN STD_LOGIC; ce_s : OUT STD_LOGIC ); END ENTITY; ARCHITECTURE rtl OF edge_sync IS SIGNAL ce_t : STD_LOGIC_VECTOR(2 downto 0); attribute altera_attribute : string; attribute altera_attribute of rtl : architecture is "-name SDC_STATEMENT ""set_false_path -to [get_registers *edge_sync:*|ce_t[0]]"""; BEGIN PROCESS (clk) BEGIN IF rising_edge(clk) THEN ce_t <= ce_t(1 downto 0) & ce; ce_s <= ce_t(1) and not ce_t(2); END IF; END PROCESS; end rtl;
[syntax=vhdl]library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HundredusCounter is
Port( clk : in STD_LOGIC;
reset : in boolean;
out_100us : out STD_LOGIC);
end HundredusCounter;
architecture Behavioral of HundredusCounter is
signal timer_1us : STD_LOGIC_VECTOR(11 downto 0):= "000000000000";
begin
process (clk)
begin
if rising_edge(clk) then
if (reset) then
timer_1us <= (others => '0');
out_100us <= '0';
elsif (timer_1us < 100) then -- use vhdl type conversion to make this integer of 3999 into a slv.
timer_1us <= timer_1us +1;
out_100us <= '1';
else
timer_1us <= (others => '0');
out_100us <= '0';
end if;
end if;
end process;
end Behavioral;[/syntax]
[syntax=vhdl]library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY edge_sync IS
PORT
(
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
ce_s : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF edge_sync IS
SIGNAL ce_t : STD_LOGIC_VECTOR(2 downto 0);
attribute altera_attribute : string;
attribute altera_attribute of rtl : architecture is
"-name SDC_STATEMENT ""set_false_path -to [get_registers *edge_sync:*|ce_t[0]]""";
BEGIN
PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
ce_t <= ce_t(1 downto 0) & ce;
ce_s <= ce_t(1) and not ce_t(2);
END IF;
END PROCESS;
end rtl;[/syntax]
[syntax=vhdl]library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Counter2_VHDL is
port( Clock_enable_B: in std_logic;
Clock: in std_logic;
Reset: in std_logic;
endVal : out std_logic;
Output: out std_logic_vector(11 downto 0));
end Counter2_VHDL;
architecture Behavioral of Counter2_VHDL is
signal temp: std_logic_vector(11 downto 0);
signal endofcount : std_logic;
begin process(Clock,Reset)
begin
if Reset='0' then
endofcount <= '1';
elsif endofcount = '1' then
temp<=(others => '0');
endofcount <= '0';
elsif(rising_edge(Clock)) then
if Clock_enable_B='1' then
if temp= 4095 then
temp<=(others => '0');
else
temp <= temp + 1;
end if;
end if;
end if;
end process;
Output <= temp;
endVal <= endofcount;
end Behavioral;[/syntax]
[syntax=vhdl]library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity d_latch_12_top is
Port ( EN : in STD_LOGIC;
clk : in STD_LOGIC;
D : in STD_LOGIC_VECTOR(11 downto 0);
Q : out STD_LOGIC_vector(11 downto 0));
end d_latch_12_top;
architecture Behavioral of d_latch_12_top is
begin
process (EN, D, clk)
begin
IF rising_edge(clk) THEN
if (EN = '1') then
Q <= D;
end if;
end if;
end process;
end Behavioral;[/syntax]
I didn´t go through the complete thread.I also have a last question, I now need to multiply the final result by 1.023, how can i do this ?
This conversation uses the word latch a lot... but I wonder if it really is the correct word. The FPGA fabric typically has DFFs, and the logic described above will become a flop with a gated clock or a muxed input. I don't see how you can latches from it.
If so.... you could simply multiply the result by 1.023 when you use a gate time of "102.3us"
all actions can and should should be performed in synchronous logic
Code VHDL - [expand] 1 2 3 4 5 6 7 8 process (clkr, clkf) begin if rising_edge(clkr) then ... elsif falling_edge(clkf) then ... end if; end process;
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