module Mux #( nmBits = 1)
( result, control, hgVal, lwVal);
output [ nmBits-1:0] result;
input control;
input [ nmBits-1:0] hgVal;
input [ nmBits-1:0] lwVal;
genvar bt;
generate
for (bt = 0; bt < nmBits; bt = bt + 1)
begin
assign result[ bt] = control ? hgVal[ bt] : lwVal[ bt];
end
endgenerate
endmodule
module UseMux( rslt, cntrl, hVal, lVal);
output [ 1:0] rslt;
input cntrl;
input [ 1:0] hVal;
input [ 1:0] lVal;
Mux mx2 #(2)( rslt, cntrl, hVal, lVal);
endmodule