Transmission gate question ?

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master_picengineer

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Hi all,
Could any one tell me where goes the bulk of the nmos and the pmos transistors in a trasmission gate.
Thanks.
 

Nmos' to lowest voltage (GND, VSS), Pmos's to highest voltage (VDD, VCC).
 

For the 65 n process what VDD=1.0/1.2/3.3 V which one I use ?
 

A.Anand Srinivasan said:
Vdd depends on the technology of your MOS device....
Click to expand...

But don't you need to consider the body effect in this condition?
 

master_picengineer said:
For the 65 n process what VDD=1.0/1.2/3.3 V which one I use ?
Click to expand...

use the one ur ckts used
 

I expect that for the 1/1.2/3.3V you would youse different devices (thick oxide). Then you would have multiple VDDs and so device types on the die. For each block you might have different VDD and so you connect the PMOS bulk to the VDD in that block. You can have 2 devices next to each other 1V and 3.3V - then the separate N-wells would be connected to 1V and to 3.3V
 

The NMOS's bulk should be connected to the least voltage available
in the operation and the PMOS's bulk shold be connected to highest
voltage in the operation . As for logic processes the least voltage typically
is GND so the NMOS's bulk should be connected to GND. And for example
if you are using in your operation VDD=1.2 you should connect bulk
of PMOS to 1.2 and if your VDD =3.3 then choose it as 3.3 but ensure that
it is the max available in the operation.

Raduga
 

Thanks for your help.
I have another question. When designing this gate using SEDIT:
Q1: A is defined as an input and B as an output or both are defined as input/output ?
Q2: For the design of the symbol the gate has 3 pins (A, B and Cconnected to Cbar) or 4 pins ?

Thanks a lot.
 

Q1, Transistors are symetrical, so the the input and output etc, depens what and how you have it connected.

Q2 Again the choice is yours, it depends how and where you create Cbar, for the circuit shouwn you will require 4 inputs.
 

Thanks Old Nick,
Could you please elaborate. the first point.
 

Transistors are symetrical, so there is no in side and out side. It is entirely up to yourself (and ofcourse the voltage levels either side, which again is up to yourself) which way the data will be transmitted.
 

AA,
According to the Mos type
NMOS bulk tie is always connected to ground in single well technology as the NMOS bulk is the substrate.
PMOS, in multi supply process we have core devices take lowest supply & I/O devices take the higher supply & so on.
best regards,
Rania
 

Thanks you all,
I analysed the problem presented in the post


I couldn't understand what is the difference when connecting the PMOS bulk to Vdd and to Vss.

Please, could someone explain.
 

master_picengineer said:
Thanks you all,
I analysed the problem presented in the post


I couldn't understand what is the difference when connecting the PMOS bulk to Vdd and to Vss.

Please, could someone explain.
Click to expand...

Hi
when in or clk in low, P-N junction of PMOS is forward biad and can effect on pullup transistor in schematic.
regards
 

Thanks,
but I still don't understand the difference between Vss and Vdd.
Any devices.
 

The device is on or off depends on the voltage between gate and substrate.
 
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