Transmission gate design in cadence

[fly1]

I tried to simulate a schematic of transmission gate in cadence. I connected the bulk of pmos to vdd and that of nmos to ground. When the transmission gate is on, output seems to be perfect but when the transmission gate is off, output is not zero. The output comes out to be half of the input in this case.
How can i improve it?

 

[crutschow]

What is the output load? You need some load or you will see parasitic signal feedthrough.

 

[fly1]

The output of the transmission gate is to be fed to an inverter