Yes, that is one way to go about doing it. The way I have done things like this in the past is to use the Matlab model to produce known inputs to stimulate the Verilog design. Then you can simulate the verilog design, collect the outputs and compare them to the Matlab outputs. Given the same inputs, the two systems should produce the same outputs. I have done this for delta sigma modulators and H.264 converter with good success.
I am not too familiar with the SPHIT algorithm, but the general approach is to think about how the various sections of the algorithm can be divided into hardware modules and split it up that way. Making block diagrams for data flow is usually a good start. The individual files for each function may already provide a good logical partition as well.