Hello all, I have a very basic question here for Integrator design. I am not too sure and hope someone can confirm.
I am currently using a PMOS Diff-Amp to implement an Integrator as shown below.
Question:
Should all transistors be in Saturation region when they are DC biased? (In the first place, am I right both input is zero? If so, that means the DC bias is 0v?)
Hello all, I have a very basic question here for Integrator design. I am not too sure and hope someone can confirm.
I am currently using a PMOS Diff-Amp to implement an Integrator as shown below.
Question:
Should all transistors be in Saturation region when they are DC biased? (In the first place, am I right both input is zero? If so, that means the DC bias is 0v?)
HI
guys
i 'm confused of the offset voltage(Vos) of a time continous intergrator.
IF i'm wrong ,plz correct me!
/ if there is a nonzero Vos in the input teminal of an intergrator , it will be intergrated to high and high , till to saturation (the output will fix at VDD or GND), and the Vos is always exits in pratical CKT, how the intergrator works ??
PLZ point out where am i wrong!
Thanks