ashrafsazid
Advanced Member level 4
Hi,
I have an ADC test bench where I have some transistor level blocks and one ctrl block. This CTRL block is written in both Verilog-A and Verilog-D code. when I perform an spectre simulation The ADC_testbench simulation is running okay, but when try to run it on AMS it gives the following error. N.B for ams simulation I am using verilog-D model of ctrl block and that didnt give me any parsing error.
I have an ADC test bench where I have some transistor level blocks and one ctrl block. This CTRL block is written in both Verilog-A and Verilog-D code. when I perform an spectre simulation The ADC_testbench simulation is running okay, but when try to run it on AMS it gives the following error. N.B for ams simulation I am using verilog-D model of ctrl block and that didnt give me any parsing error.