Traffic light program problem. pls help

THis is my full program, i am able to compile it. but it dont show my the result on a DE1 board. PLs take a look and point out my mistakes

// Main
//*********************************************************
//* Hwy = Highway , G = green , Y = yellow , R = red *
//* cnrt = country road, G = green , Y = yellow , R = red *
//*********************************************************

module traffic(
input [5:5]SW,
input CLOCK_50,
input reset,clock,
output reg [9:0] LEDR,
output reg [7:0] LEDG,
output [0:6] HEX0,HEX1,HEX2,HEX3
);
reg [2:0] state, nextstate;
reg [9:7]A = 0 ;
parameter [2:0] S0=3'b000 ;
parameter [2:0] S1=3'b001 ;
parameter [2:0] S2 =3'b010 ;
parameter [2:0] S3 = 3'b011 ;
parameter [2:0] S4 = 3'b100 ;

Displays b1(A,CLOCK_50,HEX0,HEX1,HEX2,HEX3);

always@(posedge clock or posedge reset)
begin
if(reset)
state <= S0;
else
state <=nextstate;
end

always@(state or SW[5:5])
case (state)

S0 :begin
if (SW[5:5])
begin
nextstate <= S1;
end
else
begin
A <=3'b000; // Display HrGo --> highway go
LEDG[0] <= 1; //Hwy G
LEDR[2:1] <= 0; //Hwy Y
LEDR[9] <= 0; //Hwy R
LEDG[1] <= 0; //Cnrt G
LEDR[4:3] <= 0; //Cnrt Y
LEDR[8] <= 1; //Cntr R
nextstate <= S0;
end
end

S1 :
begin
LEDG[0] <= 0; //Hwy G
LEDR[2:1] <= 1; //Hwy Y
LEDR[9] <= 0; //Hwy R
LEDG[1] <= 0; //Cnrt G
LEDR[4:3] <= 0; //Cnrt Y
LEDR[8] <= 1; //Cntr R
A<=3'b100; // show 10 and count down
nextstate <= S2;
end

S2 :begin
if ( HEX0 == 9 && HEX1 == 9 )
begin
LEDG[0] = 0; //Hwy G
LEDR[2:1] = 0; //Hwy Y
LEDR[9] = 1; //Hwy R
LEDG[1] = 0; //Cnrt G
LEDR[4:3] = 0; //Cnrt Y
LEDR[8] = 1; //Cntr R
A<=3'b101; //to show 15 and count down
nextstate = S3;
end
else
begin
LEDG[0] <= 0; //Hwy G
LEDR[2:1] <= 1; //Hwy Y
LEDR[9] <= 0; //Hwy R
LEDG[1] <= 0; //Cnrt G
LEDR[4:3] <= 0; //Cnrt Y
LEDR[8] <= 1; //Cntr R
end
end

S3 :begin
if ( (HEX0 == 9 && HEX1 == 9) && SW[5:5] )
begin
A <= 3'b010; // to blink the word "STOP" for 5sec
if((HEX0 == 9 && HEX1 == 9 && HEX2 == 9 && HEX3 == 9) && SW)
begin
LEDG[0] <= 0; //Hwy G
LEDR[2:1] <= 0; //Hwy Y
LEDR[9] <= 1; //Hwy R
LEDG[1] <= 1; //Cnrt G
LEDR[4:3] <= 0; //Cnrt Y
LEDR[8] <= 0; //Cntr R
A <= 3'b001; // display CrGo --> country go
end
else
nextstate <= S4;
end
else
nextstate <= S2;
end

S4 :begin
if ( ~SW[5:5])
begin
LEDG[0] <= 0; //Hwy G
LEDR[2:1] <= 0; //Hwy Y
LEDR[9] <= 1; //Hwy R
LEDG[1] <= 0; //Cnrt G
LEDR[4:3] <= 1; //Cnrt Y
LEDR[8] <= 0; //Cntr R
A <= 3'b100; // to show 10 and count down to 00
if( HEX0 == 9 && HEX1 == 9 )
nextstate <= S0;
else
begin
LEDG[0] <= 0; //Hwy G
LEDR[2:1] <= 0; //Hwy Y
LEDR[9] <= 1; //Hwy R
LEDG[1] <= 0; //Cnrt G
LEDR[4:3] <= 1; //Cnrt Y
LEDR[8] <= 0; //Cntr R
end
end
else
nextstate <= S3;
end
default : nextstate <= S0;
endcase

endmodule


// 1st instantiation

module Displays(
input [9:7]SW,
input CLOCK_50,
output [0:6] HEX0,HEX1,HEX2,HEX3
);

reg [9:7] A = 0;
integer counter = 0;reg clock = 0;


display1 a1(A,CLOCK_50,HEX0,HEX1,HEX2,HEX3);

always @(posedge CLOCK_50)
if ( counter >= 25000000 )
begin
counter =0;
clock <= ~clock;
end
else
counter = counter + 1;

always@(SW)
begin
case(SW)
3'b000 : A = 3'b000 ; // HrGo
3'b001 : A = 3'b001 ; // CrGo
3'b010 : A = 3'b010 ; // 5 sec
3'b100 : A = 3'b100 ; // count tensec
3'b101 : A = 3'b101 ; // count 15sec

default : A = 3'b111 ;
endcase
end
endmodule

//second instantiation


module display1(
input [9:7] SW,
input CLOCK_50,
output [0:6] HEX0,HEX1,HEX2,HEX3


);
integer countBlink = 0;
integer count5s = 0;
integer counter = 0;reg clock = 0; reg [1:0] go = 2'b00;
reg [9:7] E = 0; reg [9:7] G=0;reg [9:7] H=0;
reg [9:5] A=0; reg [9:5] B=0;reg [9:5] C = 0; reg [9:5] D=0;

display a0(D,HEX0);
display a1(C,HEX1);
display a2(B,HEX2);
display a3(A,HEX3);

always @(posedge CLOCK_50)
if ( counter >= 25000000 )
begin
counter =0;
clock <= ~clock;
end
else
counter = counter + 1;


always@(SW)

begin
if(SW[9:7] == 3'b000 ) //HrGo
begin

A = 5'b00111;
B = 5'b00110;
C = 5'b00101;
D = 5'b00100;
end
else if( SW[9:7] == 3'b001 ) // CrGo
begin
A = 5'b01000;
B = 5'b00110;
C = 5'b00101;
D = 5'b00100;
end
else if( SW[9:7] == 3'b010 ) // STOP
begin
if( E == 3'b000 )
begin
E <= 3'b110;
go <= 2'b11;
A = 5'b01001;
B = 5'b01001;
C = 5'b01001;
D = 5'b01001;
end
else if ((E !=3'b111) && (E == 3'b110 || E == 3'b101 || E == 3'b100 || E ==3'b011 || E ==3'b010 || E ==3'b001) && clock && go==2'b11 )
begin
A <= ~A;
B <= ~B;
C <= ~C;
D <= ~D;
E <= E-1;
end
else
begin
A = 5'b00011;
B = 5'b00010;
C = 5'b00001;
D = 5'b00000;
end
end

else if (SW[9:7] == 3'b100 ) //10s
begin
if (H == 3'b000)
begin
H <= 3'b001;
go <= 2'b11;
D <= 5'b01001;
C <= 5'b01010;
end
else if ( C == 5'b01010 && D == 5'b01001 && (go == 2'b11) && clock )
begin
C <=C-1;
D <=5'b10010;
end
else if ( (D >= 5'b01010) && clock && (C ==5'b01001))
D <=D-1;
else
begin
D <=5'b01001;
C <=5'b01001;
end
end

else if (SW[9:7] == 3'b101 ) //15 second
begin
if (G == 3'b000)
begin
G <= 3'b001;
go <= 2'b11;
D <=5'b01110;
C <=5'b01010;
end
else if ( C==5'b01010 && (D == 5'b01110 || D==5'b01101 || D==5'b01100 || D==5'b01011 || D==5'b01010)&&clock)
begin
D <=D-1;
end
else if ( (C == 5'b01010) && (D ==5'b01001) && clock)
begin
C <=C-1;
D <=5'b10010;
end
else if ( (C==5'b01001) && (D >= 5'b01010) && clock)
D <=D-1;
else
begin
D <=5'b01001;
C <=5'b01001;
end
end
else

begin
A <= 5'b11111 ;
B <= 5'b11111 ;
C <= 5'b11111 ;
D <= 5'b11111 ;
end
end

endmodule

//third instantiation .. shows displays

module display(
input [9:5] SW,
output reg [0:6] HEX0

);

always@(SW)
case(SW)
4'b00000 : HEX0 = 7'b0011000; //P
4'b00001 : HEX0 = 7'b0000001; //O
4'b00010 : HEX0 = 7'b0001111; //T
4'b00011 : HEX0 = 7'b0100100; //S
4'b00100 : HEX0 = 7'b0000001; //O
4'b00101 : HEX0 = 7'b0100001; //G
4'b00110 : HEX0 = 7'b1111010; //r
4'b00111 : HEX0 = 7'b1001000; //H
4'b01000 : HEX0 = 7'b0110001; //C

4'b01001 : HEX0 = 7'b0000001; //0
4'b01010 : HEX0 = 7'b1001111; //1
4'b01011 : HEX0 = 7'b0010010; //2
4'b01100 : HEX0 = 7'b0000110; //3
4'b01101 : HEX0 = 7'b1001100; //4
4'b01110 : HEX0 = 7'b0100100; //5
4'b01111 : HEX0 = 7'b0100000; //6
4'b10000 : HEX0 = 7'b0001111; //7
4'b10001 : HEX0 = 7'b0000000; //8
4'b10010 : HEX0 = 7'b0001100; //9

default : HEX0 = 7'b1111111;
endcase
endmodule


help me. ;"(

Kindly if you can elaborate on what is a DE1 board may be can get some help.
Is it a FPGA board ?

WBR
Lakshman

PS : This Code is from Looks familiar to the one in the book on verilog by samir planitkar