You cannot operate at Iout(max) and have good
dynamics, if Iout(max) is what you can get with
the gate cranked fully "on". This would then require
the control loop to be fully wound up, adding phase
lag and instability.
You need to design the pass FET, its gate drive
and the error amp so that at -rated- Iout(max),
worst case processing, worst case line and load,
the entire loop is small signal linear and within
reasonable distance of "normal operation" with
room to spare for any transient perturbation
(like load-step with overshoot).
Big FET puts big C between VIN and the control
section's back end, degrading HF PSRR. The only
remedy for that is probably a stiffer gate drive
but that costs you ground current and maybe a
baseline phase lag you didn't need more of.