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Trade-off between LDO max Iout AND PSRR

promach

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PSRR is inversely proportional to output impedance of LDO.

But Iout_max of LDO is proportional to width of output mosfet (M20) , Rds of M20 is inversely proportional to width of M20.

Given that output impedance is a parallel impedance configuration between Rds of M20 and (R1+R2), so Iout_max is proportional to output impedance of LDO.

If I need Iout_max = 3A, then my PSRR result looks very very bad.









 

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dick_freebird

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You cannot operate at Iout(max) and have good
dynamics, if Iout(max) is what you can get with
the gate cranked fully "on". This would then require
the control loop to be fully wound up, adding phase
lag and instability.

You need to design the pass FET, its gate drive
and the error amp so that at -rated- Iout(max),
worst case processing, worst case line and load,
the entire loop is small signal linear and within
reasonable distance of "normal operation" with
room to spare for any transient perturbation
(like load-step with overshoot).

Big FET puts big C between VIN and the control
section's back end, degrading HF PSRR. The only
remedy for that is probably a stiffer gate drive
but that costs you ground current and maybe a
baseline phase lag you didn't need more of.
 

promach

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The only remedy for that is probably a stiffer gate drive but that costs you ground current and maybe a
baseline phase lag you didn't need more of.
What do you exactly mean by "stiffer gate drive" ?
 

dick_freebird

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A low impedance buffer stage capable of standing
off the Miller-coupled supply "noise" out to higher
frequencies.

Your PMOS gate drive is VIN-referred. The drain is
the VOUT, and dVIN appears on the drain to couple
capacitively back to the gate. This also makes the
simple Miller compensation scheme maybe a problem
as it injects supply "noise" to the gate to be amplified
(and it may be positive gain w.r.t. VIN even though
negative feedback from FB to VOUT; the error amp
loop then has to move to cancel it, which it will do
leisurely. And PSRR in this case may be well less
than AVOL (by the positive VIN-VOUT gain) above
the pass FET / error amplifier Rout corner frequency.
 

promach

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This also makes the simple Miller compensation scheme maybe a problem as it injects supply "noise" to the gate to be amplified
I have two miller compensation. Which one were you referring to ?

By the way, I changed the feedback path in the PSRR simulation circuit to be AC 0 instead of AC 1
Then, PSRR is now at 45dB

 

promach

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And PSRR in this case may be well less than AVOL (by the positive VIN-VOUT gain) above the pass FET / error amplifier Rout corner frequency.
What do you exactly mean by Rout corner frequency ?
 

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