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Toplevel Verilog with VHDL entities

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niklar

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Hello,

I have several VHDL entities that I would like to instantiate in a toplevel Verilog file. How can this be done?

Thanks
 

tahiti

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it depends on a simulator you use. if you use modelsim, check mixed simulation chapters of user guide

tahiti
 

verilog

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In addition, it depends on synthesizers
 

niklar

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Well, we are trying to run Design Analyzer of Synopsis. There is a relativly good tutorial on Verilog design.

However, the code we have is written in VHDL. Thus, we either have to "force" Design Analyzer deal with it or make a toplevel verilog code and somehow instatiate VHDL entities in it. :roll:

The problem with VHDL is that we can not find were we have to specify the technology (cmosp18). It keeps the default one - GTECH (general technology?)
 

my_garden

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The men*or's FPGAV can do this work. And spec*rum or X-Vhdl can transfer the two word.
 

always@smart

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niklar said:
Well, we are trying to run Design Analyzer of Synopsis. There is a relativly good tutorial on Verilog design.

However, the code we have is written in VHDL. Thus, we either have to "force" Design Analyzer deal with it or make a toplevel verilog code and somehow instatiate VHDL entities in it. :roll:

The problem with VHDL is that we can not find were we have to specify the technology (cmosp18). It keeps the default one - GTECH (general technology?)


------------------------------------------------------------

Hi niklar,

I'm not sure if you face this promble or not.Try to edit the ".synopsys_dc.setup" in the directory where you run the Design Analyzer!!


set target_library "slow.db " #this is your target library file
set link_library "* slow.db " #this is your library file,typically it is as same as target library file
set symbol_library "core.sdb " #this is you symbol library

set search_path "$search_path /export/home/Synopsys/libfile ." #the path for the 1st and 2nd file shown abouve

set search_path "$search_path /export/home/Synopsys/symbol" #the path for the 3rd file shown above
-----------------------------------------------------

Hope this will help you

Best Regards :oops:
 

always@smart

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niklar said:
Well, we are trying to run Design Analyzer of Synopsis. There is a relativly good tutorial on Verilog design.

However, the code we have is written in VHDL. Thus, we either have to "force" Design Analyzer deal with it or make a toplevel verilog code and somehow instatiate VHDL entities in it. :roll:

The problem with VHDL is that we can not find were we have to specify the technology (cmosp18). It keeps the default one - GTECH (general technology?)


------------------------------------------------------------

Hi niklar,

I'm not sure if you face this promble or not.Try to edit the ".synopsys_dc.setup" in the directory where you run the Design Analyzer!!


set target_library "slow.db " #this is your target library file
set link_library "* slow.db " #this is your library file,typically it is as same as target library file
set symbol_library "core.sdb " #this is you symbol library

set search_path "$search_path /export//Synopsys/libfile ." #the path for the 1st and 2nd file shown above

set search_path "$search_path /export//Synopsys/symbol" #the path for the 3rd file shown above
-----------------------------------------------------

Hope this will help you

Best Regards :oops:
 

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