to "draw" the schematics from the vhdl code (kind of manual synthesis).

[pierre13]

Hello !!

I would like to be able to "draw" from the vhdl code, the schematics (Flip-Flop Combinatorial Logic, inputs/outputs ...).
Does someone has an example with 2-3 FF and some logic ?
I already got ModelSim, so I have some vhdl code and testbench, but the "synthesis" step is not very familiar to me. I am trying to get Xilinx Suite to make the synthesis of my vhdl code, to understand it, but as far as now, I have some issue with the installation.

Thanks for any help,
Pierre

 

[dftrtl]

What exactly your are looking for ?

 

[pierre13]

Hi !!
An example, because I don't find any on the Internet, and my school classes doesn't help me so much, because they just deal with vhdl coding (and not vhdl coding with a synthetizable way of doing).
Can you help me ?
Pierre

 

[soloktanjung]

What kind of example do you need? This tutorial for synthesizing VHDL code using Xilinx ISE: **broken link removed**

Thanks.

 

[pierre13]

Hello !
Sorry for this late return.
I have used Xilinx ISE and I do the SYnthesis of the vhdl code. Then, I can see the RTL schematic which corresponds.
I wanted to be able, from the vhdl code, to say what are the ressources I need.

Regards,
Pierre