To create a more efficient two dimensional vhdl arrays table

Hi,
Does anybody advise how to create a efficient vhdl 2 dimensional array table? For example for the below vhdl code:-

For each case statement, I have key in the cntdata constants. If I have hundreds or thousands of cntdata constants, does anybody know how to create more effciently(eg. without actual writing(or keyin) in constants for the cntdata?

library ieee;
use ieee.std_logic_1164.all;
entity ddc is
port(
clk : in std_logic;
reset : in std_logic;

EnClk : out std_logic;
DQ_A : out std_logic;
CSn_A : out std_logic;

Msbfirst : out std_logic;
Smode : out std_logic;
Mode : out std_logic;
start : out std_logic);
end entity;
architecture rtl of ddc is

type state_type is (s0, s1, s2, s3, s4, s5, s6, s7, s10, nil);
signal state : state_type;
signal ndelay,ndelay1 : integer range 0 to 150;
signal index : integer range 0 to 150;
signal bitindex : integer range 0 to 23;
signal dcnt : integer range 0 to 8000;
signal DQ,CSn: std_logic;
signal cnt,cinttot: integer;
signal cntdata: integer;
signal sig1,clkout1: std_logic;
signal d3,d4: std_logic_vector(7 downto 0);
begin
-- Logic to advance to the next state
process (clk, reset)
begin
if reset = '0' then
state <= s0;
index<=0;
bitindex<=9;

EnClk<='0';
CSn<='1';
DQ<='0';
ndelay<=0;
ndelay1<=0;
d3<= (others => '0');

cntdata<=1;
sig1<='0';

Msbfirst<='1';
Smode<='0';
Mode<='1';
start<='0';

dcnt<=0;

elsif (rising_edge(clk)) then
start<='0';
case cntdata is

when 1 => d3 <= x"01";
when 2 => d3 <= x"13";
when 3 => d3 <= x"80";
when 4 => d3 <= x"01";
when 5 => d3 <= x"3F";
when 6 => d3 <= x"CF";
when 7 => d3 <= x"03";
when.........................
...
...
when 296 => d3 <= x"00";
when others =>

end case;



case state is
when s0=>
if sig1 = '0' then
CSn<='1';
EnClk<='0';

Smode<='1';
Msbfirst<='0';
sig1<='0';

index<=0;
bitindex<=9;
Mode<='0';


state <= s1;

dcnt<=0;

end if;

when s5=>
EnClk<='1';
clkout1<='1';
ndelay<=ndelay+1;
if ndelay =2 then
ndelay<=0;
state<=s7;
end if;
when s7=>
EnClk<='0';
clkout1<='0';
ndelay<=ndelay+1;
if ndelay =2 then
ndelay<=0;
state<=s1;
end if;
CSn<='0';
Mode<='0';

when s1=>

EnClk<='0';

DQ_A<=d3(9-bitindex);
bitindex<=bitindex-1;

index<=index+1;
if bitindex =1 then
EnClk<='0';
state <= s2;
DQ_A<='0';
else
ndelay<=0;
state<=s5;
end if;
when s2=>

CSn<='1';
Mode<='1';
state <= s3;

when s3=>
DQ_A<='0';
state <= s10; --s4

when s10=>
dcnt <= dcnt + 1;
if dcnt = 4999 then
state <= s4;
else
state <= s3;
end if;

when s4=>
DQ_A<='0';
index<=index+1;
if index =1 then
state <= s6;
-- state <= s0;
end if;

when s6=>

if cntdata<296 and sig1 = '0' then
cntdata <= cntdata +1;
state <= s0;
else
state <=s0;
sig1 <= '1';

end if;
Smode<='1';
Msbfirst<='0';
start<='1';

when nil=>

end case;

end if;
end process;

CSn_A<=CSn;
end rtl;