Tips on how to implement video ram

[hdhzero]

Hi everyone,

Here are the main and resumed questions:
- can SDR SDRAM run at any frequency?
- if I was supposed to assert a signal on clock N, but I assert on clock N+1, will the SDR SDRAM be damaged?

Any other suggestions on how to implement videoram are welcome!

Here is the full context:

I am trying to create a VGA controller + bitmapped memory. My problem is how to implement
bitmapped/video ram.

My FPGA can output a 12 bit pixel for VGA. Some math:
640x480x12 = 3686400 bits

This is a lot of bits for my FPGA's block ram, but I have a SDR SDRAM that I never used and I
am afraid to use it because:

1 - I have no idea what frequencies the SDR SDRAM can run: (100MHz? 133MHz? 10MHz? or whatever?)
Or: are there min and max frequency operation for sdram?

2 - I already have a SDR SDRAM controller, but as I never used it, I fear that a signal asserted on the wrong
time can damage my SDR SDRAM. When I implement a wrong FSM in VHLD, it just produces wrong results, but
it does not damage my FPGA. If my SDR SDRAM controller has a few bugs, could it damage the SDR SDRAM?

Example: the SDR SDRAM is refreshing and, because of a bug, the sdram controller tries to perform a write operation or
a read operation
Example2: I should assert a signal in clock N, but assert it in clock N+1.

3 - The sdram controller is working is simulations, but with a different memory model from the one used in my FPGA.
what are the chances of not working with my sdram?

Thanks to everyone who read this carefully