Tips and information for entering the 90nm technology

[rajath]

Hi all,
I'm about to embark on a project where I'll be required to design LDo's and switching regulators. I've decided to do it in 90nm technology, since it can be easily integrated with the current digital blocks, if needed. Does anyone have experience/horror stories
with regard to this technology? How easy will it be for me to design BG references, linear regulators and switched capacitor blocks in 90nm? If anybody has any reference material, and can pass it on, I'll be really grateful.

thanks!
rajath

 

[ccw27]

Re: Entering 90nm

I am still in 0.15 um technology, but from what I heard from my device team is that for 0.13um and below there is gate leakage (modeled in spice) and LOD effect (precautions must be taken during layout). I am sure there are more subtleties.

 

[selvaraja]

Re: Entering 90nm

Hi

it will be challenging designing those in 90nm ..... lot issue is concern desiging in 90nm ...good luck

 

[skal81]

Re: Entering 90nm

You could refer to:
- Analog Circuits in Ultra-Deep Submicron CMOS, A.J. Annema, B. Nauta & al.
(JSSC vol 40,p132, Janv. 2005)
- A 1V 88dB 20kHz ΣΔ Modulator in 90nm CMOS, L. Yao, M. Steyaert, W. Sansen
(ISSCC 2004 pp80-81 / JSSC Dec 2004)
The first is about general consideration, the second a practical design exemple.
(Sorry I don't have the PDF).
Good luck

 

[mreza1355]

Re: Entering 90nm

Analog Design in VDSM (Very Deep Submicron)

Sansen

 

[mreza1355]

Re: Entering 90nm

ISSCC sansen

 

[piao]

Entering 90nm

I think it is also up to the LDO SPEC, most people like to use 0.6u~0.25um to design power management circuit.