[SOLVED] Tiny encription algorithm (TEA) in VHDL need help

[emperror123]

hi guys

currently i m facing problem in implementing TEA in VHDL. the program can be compile successfully, but unfortunately the data has no output, i have no idea why.

below are my coding

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity TEA is
port(
clk : in std_logic;
input : in std_logic_vector (63 downto 0);
key : in std_logic_vector (127 downto 0);
encript, decript : out std_logic_vector (63 downto 0)
);
end TEA;

architecture TEA of TEA is
signal k0, k1, k2, k3: std_logic_vector(31 downto 0);
signal n: integer:=0;

begin
	k0<=key(127 downto 96);
	k1<=key(95 downto 64);
	k2<=key(63 downto 32);
	k3<=key(31 downto 0);
process (clk, input)
variable z, z1, z2,z3,zt,y, y1, y2, y3, yt: std_logic_vector (31 downto 0);
variable sum: std_logic_vector (31 downto 0) ;
variable delta: std_logic_vector (31 downto 0) ;

begin

	delta := x"9E3779B9";
	sum := x"00000000";
if rising_edge(clk) then
	
	if (n=0) then
	y:= input(63 downto 32);
	z:= input(31 downto 0);
	
	else if (n=32) then
	
	sum:=delta(26 downto 0) & "00000";
	end if;

if (n<32) then
	sum:=sum+delta;
	
	z1:= ((z(27 downto 0) &"0000")+k0);
	z2:= (z+sum);
	z3:= (("00000"& z(31 downto 5))+k1);
	zt:= z1 xor z2 xor z3;
	y := y+zt;

	y1:= ((y(27 downto 0) &"0000")+k2);
	y2:= (y+sum);
	y3:= (("00000"& y(31 downto 5))+k3);
	yt:= y1 xor y2 xor y3;
	z := z+yt;

	encript <= y&z;

else if (n<64) then
	y1:= ((y(27 downto 0) &"0000")+k2);
	y2:= (y+sum);
	y3:= (("00000"& y(31 downto 5))+k3);
	yt:= y1 xor y2 xor y3;
	z := z-yt;

	z1:= ((z(27 downto 0) &"0000")+k0);
	z2:= (z+sum);
	z3:= (("00000"& z(31 downto 5))+k1);
	zt:= z1 xor z2 xor z3;
	y := y-zt;

	sum := sum-delta;
	Decript <= y&z;
end if;
end if;
	n<=n+1;
end if;
end if;
end process;
end TEA;

the warning showed

Warning: Feature LogicLock is not available with your current license
Warning: No exact pin location assignment(s) for 321 pins of 321 total pins
Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Warning: Found 128 output pins without output pin load capacitance assignment
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Warning: Found pins functioning as undefined clocks and/or memory enables
	Info: Assuming node "clk" is an undefined clock

hope u all can help me out

 

[ads-ee]

Given the way the code goes through the if statements n never increments.

Just an observation, but your code looks like you are writing a software program and aren't trying to describe a hardware circuit. I've noticed that those with heavy software backgrounds tend to use VHDL variables a lot, while first learning VHDL. I've only used them on a few occasions mostly for code clarity and for memory arrays (I'm a hardware engineer). You should stick with signals for the majority of synthesizable code, and reserve the use of variables for the aforementioned clarifying cases, memory arrays, and in testbenches.

Here is your code formatted correctly given VHDL syntax rules. I don't think you've formatted the code correctly and you used else if in place of elsif.

---

Code VHDL - [expand]
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process (clk, input)
        variable z, z1, z2,z3,zt,y, y1, y2, y3, yt: std_logic_vector (31 downto 0);
        variable sum: std_logic_vector (31 downto 0) ;
        variable delta: std_logic_vector (31 downto 0) ;
 
    begin
 
        delta := x"9E3779B9";
        sum := x"00000000";
        if rising_edge(clk) then
            if (n=0) then
                y:= input(63 downto 32);
                z:= input(31 downto 0);
            else  -- I think this is was supposed to be an elsif (n=32) then
                if (n=32) then
                    sum:=delta(26 downto 0) & "00000";
                end if;
 
                if (n<32) then
                    sum:=sum+delta;
 
                    z1:= ((z(27 downto 0) &"0000")+k0);
                    z2:= (z+sum);
                    z3:= (("00000"& z(31 downto 5))+k1);
                    zt:= z1 xor z2 xor z3;
                    y := y+zt;
 
                    y1:= ((y(27 downto 0) &"0000")+k2);
                    y2:= (y+sum);
                    y3:= (("00000"& y(31 downto 5))+k3);
                    yt:= y1 xor y2 xor y3;
                    z := z+yt;
 
                    encript <= y&z;
 
                else  -- I also suspect this was also supposed to be and elsif
                    if (n<64) then
                        y1:= ((y(27 downto 0) &"0000")+k2);
                        y2:= (y+sum);
                        y3:= (("00000"& y(31 downto 5))+k3);
                        yt:= y1 xor y2 xor y3;
                        z := z-yt;
 
                        z1:= ((z(27 downto 0) &"0000")+k0);
                        z2:= (z+sum);
                        z3:= (("00000"& z(31 downto 5))+k1);
                        zt:= z1 xor z2 xor z3;
                        y := y-zt;
 
                        sum := sum-delta;
                        Decript <= y&z;
                    end if;
                end if;
                n<=n+1;
            end if;
        end if;
    end process;

---

 

[emperror123]

hi ads

thank for ur info, the VHDL now function but the problem now is i unable to decripted it, no idea am i wrong on my coding or wat

 

[FvM]

I think the modification does only 31 instead of 32 rounds. The original version is apparently intended to perform the first round in the same clock cycle after the encrypt/decrypt setup.

I also can't relate the below operation to the TEA algorithm.

sum:=delta(26 downto 0) & "00000";

Just an observation, but your code looks like you are writing a software program and aren't trying to describe a hardware circuit.

Yes, obviously the standard C-code implementation has been directly "translated" into VHDL. https://en.wikipedia.org/wiki/Tiny_Encryption_Algorithm

 

[emperror123]

i have found the solution, thank for the help

 

[code_slave]

Should not be using TEA for encryption anyway….
Several serious flaws and weaknesses were found in the algorithm making it trivial to 'break'

 

[FvM]

Should not be using TEA for encryption anyway….
Several serious flaws and weaknesses were found in the algorithm making it trivial to 'break'.

True indeed. But this is rather an excercise problem than a real encryption application. TEA is well suited for an excercise due to it's simplicity but involves critical points how to effectively translate a sequential algorithm into parallel hardware. Unfortunately we didn't see a convincing solution within this thread yet.