You use constraints, if you don't use constraints then the tools will do an extremely poor job of meeting any timing (as there isn't any requirements). I guarantee it will be very slow compared to using constraints, unless the design is so simple that it always implements the same way regardless of the clock constraint or lack thereof.
If you don't care about timing closure then add a clock constraint of 1 MHz and the STA report will show the clock frequency achievable (above 1 MHz). Unlike Quartus tools ISE and Vivado doesn't seem to give any timing summary for unconstrained designs.