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timing simulation error

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Tayyab Umair

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expecting type ieee.std_logic_1164.std_logic.

hi every body

i am having a problem while doin timing simulation of my vhdl code of viterbi decoder.
errors are
** Error: new_testbnch.vhd(57): Signal "code_rate" is type ieee.numeric_std.unsigned; expecting type ieee.std_logic_1164.std_logic.
# ** Error: new_testbnch.vhd(57): Signal "data_i" is type ieee.numeric_std.unsigned; expecting type ieee.std_logic_1164.std_logic.
# ** Error: new_testbnch.vhd(58): Signal "data_q" is type ieee.numeric_std.unsigned; expecting type ieee.std_logic_1164.std_logic.
# ** Error: new_testbnch.vhd(58): Signal "br_mat_out" is type ieee.numeric_std.unsigned; expecting type ieee.std_logic_1164.std_logic.
# ** Error: new_testbnch.vhd(58): Signal "dec_out_en" is type ieee.std_logic_1164.std_logic; expecting type ieee.numeric_std.unsigned.
# ** Error: new_testbnch.vhd(58): Signal "valid" is type ieee.std_logic_1164.std_logic; expecting type ieee.numeric_std.unsigned.
# ** Error: new_testbnch.vhd(58): Signal "dec_rdy" is type ieee.std_logic_1164.std_logic; expecting type ieee.numeric_std.unsigned.
# ** Error: new_testbnch.vhd(58): Signal "dec_out" is type ieee.std_logic_1164.std_logic; expecting type ieee.numeric_std.unsigned.
# ** Error: new_testbnch.vhd(175): VHDL Compiler exiting
# ** Error: C:/Modeltech_6.2g/win32pe/vcom failed.
to tel more abt it i am using unsigned type in my code for which i have also added ieee.numeric_std.unsigned library.n i have also made changes to tim-sim.vhd file....bt of no avail:
i don have any idea abt these errors
can anybdy plz tel me abt these errors that why these come duirng timing simulation of a vhdl code.me badly waitng 4 nice replies....
 

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