Re: Timing delays
I meant, design should meet timing in STA tools, otherwise you would anyway see those violations in your simulations ( after annotating SDF generated by same STA tools) and simulation would fail.
Simulator can be any - VCS/NC-verilog/Modelsim etc, All support SDF backannotation, only the switches/options to do so are different.
I haven't worked in xilinx-ISE, but I am hoping that it would also support SDF backannotation. But since its a integrated tool, it might give you smarter way of simulating timing delays.