Hi,
Even without timing constraints the compiler will make your design to work.
But if you (your application) requires to keep some timing, you have to tell the compiler about it.
Example:
* Blinking a LED with 1Hz. .. will work in either case, since even in worst case the FPGA is way faster.
* but if you want to access to an external SRAM with 50 million write cycles per second...you need to ensure proper SRAM timing.
So you have to read the SRAM datasheet, find out the timing requiremt and tell the compiler about it.
Now the compiler will translate your design to meet the desired function, then it will test whether the "compiled solution" will meet the timing requirements. If not, it will run a new complation with some optimisation to meet your timing requirement. Maybe it has to do a lot of compile runs. In best case it finds a suitable solution, otherwise it will tell you that it is impossible to meet the timing requirements. And it will tell you which path does not meet the requirement.
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Usually one of the first things when you start an FPGA design is to decide the requirements. Not only functional, but also with timing.
And as so often. Requirements need to be very clear. Phrases like "a faster clock" won´t work.
Klaus