pierre13
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Hello,
using a characterization tool I am defining the measurement results to be written in a .lib for the RETENTION cells.
Example : RETENTION Flip-Flop (inputs : D, RET, outputs : Q, clock : CP).
My question : what are the timing/constraint/mpw measurements in the .lib, and especially the ones linked to the RET signal ?
Is there a RET_CP_setup in order to propagate the right data during the wake-up sequence ?
classic .lib for a FF :
Example :
Power-Down sequence : first, CP is switched OFF, then RET signal is switched to ON state just before power-down (VDD OFF) to save the internal data (between the 2 latches of the FF) (example : save to a baloon latch).
Then, the power-down (VDD OFF) occurs).
Wake-up sequence : first, VDD is switched-on, then RET signal is realeased (so the saved data move from the baloon latch to the 2nd latch of the FF) and finally, CP is switched on again to propagate the saved data on the pin Q.
Thanks for any help.
P.
using a characterization tool I am defining the measurement results to be written in a .lib for the RETENTION cells.
Example : RETENTION Flip-Flop (inputs : D, RET, outputs : Q, clock : CP).
My question : what are the timing/constraint/mpw measurements in the .lib, and especially the ones linked to the RET signal ?
Is there a RET_CP_setup in order to propagate the right data during the wake-up sequence ?
classic .lib for a FF :
Code:
pin(CP) {
[INDENT][/INDENT]timing {
[INDENT][INDENT][/INDENT][/INDENT]mpw_high
[INDENT][INDENT][/INDENT][/INDENT]mpw_low
}
}
pin(D) {
[INDENT][/INDENT]timing {
[INDENT][/INDENT]related_pin : CP
[INDENT][/INDENT]timing_label : D_CP_HOLD (fall_constraint/rise_constraint)
[INDENT][/INDENT]timing_label : D_CP_SETUP (fall_constraint/rise_constraint)
}
}
pin(Q) {
[INDENT][INDENT][/INDENT][/INDENT]timing {
[INDENT][INDENT][/INDENT][/INDENT]related_pin : CP
[INDENT][INDENT][/INDENT][/INDENT]cell_rise/cell_fall
[INDENT][INDENT][/INDENT][/INDENT]rise/fall_transition
}
}
Example :
Power-Down sequence : first, CP is switched OFF, then RET signal is switched to ON state just before power-down (VDD OFF) to save the internal data (between the 2 latches of the FF) (example : save to a baloon latch).
Then, the power-down (VDD OFF) occurs).
Wake-up sequence : first, VDD is switched-on, then RET signal is realeased (so the saved data move from the baloon latch to the 2nd latch of the FF) and finally, CP is switched on again to propagate the saved data on the pin Q.
Thanks for any help.
P.
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