Nov 9, 2009 #1 N nice2meet_you Newbie level 2 Joined Nov 5, 2009 Messages 2 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Location USA Activity points 1,292 Hi guys, If a system has some asynchronous inputs to the FPGA (such as push buttons, or an interface from another processor that runs at different speed than the FPGA). There is no associated input clock for these signals. How should I set the input timing constraints? thank you
Hi guys, If a system has some asynchronous inputs to the FPGA (such as push buttons, or an interface from another processor that runs at different speed than the FPGA). There is no associated input clock for these signals. How should I set the input timing constraints? thank you