nice2meet_you
Newbie level 2
Hi guys,
If a system has some asynchronous inputs to the FPGA (such as push buttons, or an interface from another processor that runs at different speed than the FPGA). There is no associated input clock for these signals.
How should I set the input timing constraints?
thank you
If a system has some asynchronous inputs to the FPGA (such as push buttons, or an interface from another processor that runs at different speed than the FPGA). There is no associated input clock for these signals.
How should I set the input timing constraints?
thank you
