May 4, 2010 #1 M madhusudhan_prabhu Newbie level 4 Joined Apr 15, 2008 Messages 7 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,322 Hi All, I want to know what are timing checks in testbenches (VHDL, Verilog or System C)? types of timing checks that exists? How to implement it in any one of the above mentioned HDL languages? Thanks, Madhu
Hi All, I want to know what are timing checks in testbenches (VHDL, Verilog or System C)? types of timing checks that exists? How to implement it in any one of the above mentioned HDL languages? Thanks, Madhu