Timing and functional simulation results for a ff with asynch set don't match.

[kemalkemal]

Hi
I'm using Quartus 2 13.1 web edition and modelsim altera starter edition 10.1d. I have a terasic D0 board which i run my codes after simulations. My code is like that

library ieee;
use ieee.std_logic_1164.all;
entity DD is 
port (clk,X :in std_logic; 
        asyncset : in std_logic; -- D'den gelen out1 sinyali 
        Y:out std_logic);
        end entity DD;
architecture behav of DD is
begin
process(clk,asyncset) begin     
    if asyncset = '1' then
        Y<='1';
        elsif rising_edge (clk) then 
        Y<= not X;
end if;
end process;
end architecture behav;

After functional simulation every thing seems ok but when i execute timing simulation it works completely opposite.
Functional Sim
https://obrazki.elektroda.pl/5436091700_1417085337.jpg
Timing Sim
https://obrazki.elektroda.pl/6451318800_1417085385.jpg

What tools should i use to fix this situation? And any advice for this problem ? Thanks.

 

[sharath666]

The functional simulation itself is incorrect. Y should be delayed by 1 clock compared to X. At the rising edge of clk, when X is sensed as 1, Y should go 0 from that point onwards. Same situation when X is sensed as 0. I hope you are getting it.
Seems to be a delta delay issue. You can resolve it by adding the after clause to Y<=X statement. A delay of 0 would also do. The timing aim looks bizarre. But I better not look at it till you correct the functional case.

 

[std_match]

Please show the test bench code. It seems that X is generated in a bad way.

 

[ads-ee]

It's a delta time issue, I've seen this before in poorly design testbenches that use a bunch of sequentially delayed statements to generate both the clock and the data.