anwei7208
Junior Member level 1
After assemble the partitions, I tried to do static timing analysis over the whole design, but it the timing report shows 0 delays in the buffers of clock paths. It seems that the tool didn't consider the wire load while computing timing. In the timing analysis of each individual partition, however, the path delays looked fine. Can anyone tell me why and how to fix? Did I miss something after assemble the partitions? Thanks very much.