dayana42200
Junior Member level 3
Hi all.
Im using Xilinx ISE Design Suite 14.7 for my timing analysis using a constraint shown below.
After PAR there were errors on the timing analysis based on the timing constraint above. Below shows some of the error example
I need help and guidance based on the experience to improve the timing issue.
Thank you very much.
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I add some timing analysis details for slack no .1
Im using Xilinx ISE Design Suite 14.7 for my timing analysis using a constraint shown below.
NET "Clk" TNM_NET = "Clk";
TIMESPEC "TS_Clk" = PERIOD "Clk" 40 ns HIGH 50%;
OFFSET = IN 15 ns VALID 17 ns BEFORE Clk;
OFFSET = OUT 8 ns AFTER Clk;
After PAR there were errors on the timing analysis based on the timing constraint above. Below shows some of the error example
I need help and guidance based on the experience to improve the timing issue.
Thank you very much.
- - - Updated - - -
I add some timing analysis details for slack no .1