Dec 22, 2018 #1 D dayana42200 Junior Member level 3 Joined Feb 9, 2018 Messages 31 Helped 0 Reputation 0 Reaction score 1 Trophy points 6 Activity points 315 Hi all. Im using Xilinx ISE Design Suite 14.7 for my timing analysis using a constraint shown below. NET "Clk" TNM_NET = "Clk"; TIMESPEC "TS_Clk" = PERIOD "Clk" 40 ns HIGH 50%; OFFSET = IN 15 ns VALID 17 ns BEFORE Clk; OFFSET = OUT 8 ns AFTER Clk; Click to expand... After PAR there were errors on the timing analysis based on the timing constraint above. Below shows some of the error example I need help and guidance based on the experience to improve the timing issue. Thank you very much. - - - Updated - - - I add some timing analysis details for slack no .1
Hi all. Im using Xilinx ISE Design Suite 14.7 for my timing analysis using a constraint shown below. NET "Clk" TNM_NET = "Clk"; TIMESPEC "TS_Clk" = PERIOD "Clk" 40 ns HIGH 50%; OFFSET = IN 15 ns VALID 17 ns BEFORE Clk; OFFSET = OUT 8 ns AFTER Clk; Click to expand... After PAR there were errors on the timing analysis based on the timing constraint above. Below shows some of the error example I need help and guidance based on the experience to improve the timing issue. Thank you very much. - - - Updated - - - I add some timing analysis details for slack no .1
Dec 22, 2018 #2 ads-ee Super Moderator Staff member Joined Sep 10, 2013 Messages 7,944 Helped 1,822 Reputation 3,654 Reaction score 1,808 Trophy points 1,393 Location USA Activity points 60,207 10x the period you requested!? Did you notice you have 632 levels of logic, there isn't a technology anywhere that can run at 25MHz with that many levels of logic. You better show us your code you obviously didn't account for levels of logic between sequential elements anywhere in your code..
10x the period you requested!? Did you notice you have 632 levels of logic, there isn't a technology anywhere that can run at 25MHz with that many levels of logic. You better show us your code you obviously didn't account for levels of logic between sequential elements anywhere in your code..
Dec 22, 2018 #3 D dayana42200 Junior Member level 3 Joined Feb 9, 2018 Messages 31 Helped 0 Reputation 0 Reaction score 1 Trophy points 6 Activity points 315 View attachment DNASeqFull.rarView attachment DNASeqFull.rar Im so sorry I have 21 files. Im designing a systolic array. Systolic array consists of an array Processing Element. So in my design Ive 114 PEs. So my design is very large.
View attachment DNASeqFull.rarView attachment DNASeqFull.rar Im so sorry I have 21 files. Im designing a systolic array. Systolic array consists of an array Processing Element. So in my design Ive 114 PEs. So my design is very large.
Dec 23, 2018 #4 barry Advanced Member level 7 Joined Mar 31, 2005 Messages 6,333 Helped 1,194 Reputation 2,400 Reaction score 1,389 Trophy points 1,393 Location California, USA Activity points 34,480 632 logic levels??? THAT sounds like a problem. I think you need some pipelining. Oops, just saw Ads's post.
632 logic levels??? THAT sounds like a problem. I think you need some pipelining. Oops, just saw Ads's post.
Dec 24, 2018 #5 V vGoodtimes Advanced Member level 4 Joined Feb 16, 2015 Messages 1,089 Helped 307 Reputation 614 Reaction score 303 Trophy points 83 Activity points 8,730 There should be some pipeline register stages in the systolic array.